ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 33 of 196
REGISTER SUMMARY: ADDITIONAL REGISTERS
The CPU accesses these additional registers over a die to die interface (D2D) which increases the execution times of ldr and str instructions.
The 32 bit MMRs have addresses of 0x40087xxx and take 8 CPU cycles at 80 MHz to execute. The 8 bit MMRs have addresses of 0x40081xxx
and take 5 CPU cycles at 80 MHz to execute.
Table 20. Register Summary
Address
Name
Description
Reset
RW
0x40081400
IBUFCON
InBuf control bit
0x000F
RW
0x40087830
AFETEMPC
Temperature sensor configuration register
0x00
RW
0x40087834
AFEREFC
Reference configuration register
0x00
RW
REGISTER DETAILS: ADDITIONAL REGISTERS
InBuf Control Bit Register
Address: 0x40081400, Reset: 0x000F, Name: IBUFCON
Table 21. Bit Descriptions for IBUFCON
Bits
Bit Name
Description
Reset
Access
[15:4]
RESERVED
Reserved.
0x0
RW
[3:2]
IBUF_PD
Power down P/N InBuf separately.
0x3
RW
00: both sides powered on
01: N side powered down
10: P side powered down
11: both sides powered down
[1:0]
IBUF_BYP
Bypass P/N InBuf separately.
0x3
RW
00: bypass none sided
01: N side bypassed
10: P side bypassed
11: bypass both
Temperature Sensor Configuration Register
Address: 0x40087830, Reset: 0x00, Name: AFETEMPC
Table 22. Bit Descriptions for AFETEMPC
Bits
Bit Name
Description
Reset
Access
[7:2]
RESERVED
Reserved.
0x0
R
1
CHOP
Temperature sensor chopping enable. Do not use chopping mode
together with the sequencer.
0x0
RW
0: disable chopping mode
1: enable chopping mode
0
PD
Temperature sensor power down.
0x0
RW
0: power up temperature sensor
1: power down temperature sensor
