ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 63 of 196
Example Code: Define DMA Structures
To define DMA structures,
memset(dmaChanDesc,0x0, sizeof(dmaChanDesc)); // Set up the DMA base address pointer register.
uiBasPtr = (unsigned int)&dmaChanDesc;
// Set up the DMA base pointer.
pADI_DMA->DMACFG = 1;
// Enable DMA controller
pADI_DMA->DMAPDBPTR = uiBasPtr;
CONTROL DATA CONFIGURATION
For each DMA transfer, the CHNL_CFG memory location provides the control information for the DMA transfer to the controller.
Table 74. Control Data Configuration
Bits
Name
Description
[31:30]
DST_INC
Destination address increment. The address increment depends on the source data width as follows:
Source Data Width
DST_INC
Destination Address Increment
Byte
00
Byte.
01
Half word.
10
Word.
11
No increment. Address remains set to the value that the
DST_END_PTR memory location contains.
Half Word
00
Reserved.
01
Half word.
10
Word.
11
No increment. Address remains set to the value that the
DST_END_PTR memory location contains.
Word
00
Reserved.
01
Reserved.
10
Word.
11
No increment. Address remains set to the value that the
DST_END_PTR memory location contains.
[29:28]
DST_SIZE
Size of the destination data. Must match SRC_SIZE.
00: byte.
01: half word.
10: word.
11: reserved.
[27:26]
SRC_INC
Source address increment. The address increment depends on the source data width as follows:
Source Data Width
DST_INC
Source Address Increment
Byte
00
Byte.
01
Half word.
10
Word.
11
No increment. Address remains set to the value that the
SRC_END_PTR memory location contains.
Half Word
00
Reserved.
01
Half word.
10
Word.
11
No increment. Address remains set to the value that the
SRC_END_PTR memory location contains.
Word
00
Reserved.
01
Reserved.
10
Word.
11
No increment. Address remains set to the value that the
SRC_END_PTR memory location contains.
