UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 138 of 196
Polling the status flag is processor intensive and not typically used unless the system can tolerate the overhead. Interrupts can be disabled
using the COMIEN register.
Writing COMTX when it is not empty or reading COMRX when it is not full produces incorrect results and should not be done. In the
former case, COMTX is overwritten by the new word, and the previous word is never transmitted. In the latter case, the previously
received word is read again. Both of these errors must be avoided in software by correctly using either interrupts or status register polling.
These errors are not detected in hardware.
Enable/Disable Bit
Before the
enters power-down mode, it is recommended to disable the serial interfaces. A bit is provided in the UART
control register to disable the UART serial peripheral. This bit disables the clock to the peripheral. When setting this bit, care must be
taken in software that no data is being transmitted or received. If this bit is set during communication, the data transfer does not
complete; the receive or transmit register contains only part of the data.
Interrupts
The UART peripheral has one interrupt output to the interrupt controller for both Rx and Tx interrupts. The COMIIR register must be
read by software to determine the cause of the interrupt. Note that in DMA mode the break interrupt is not available.
In I/O mode when receiving, the interrupt is generated for the following cases:
•
COMRX full
•
Receive overflow error
•
Receive parity error
•
Receive framing error
•
Break interrupt (UART RxD held low)
•
COMTX empty
Buffer Requirements
This UART is double buffered (holding register and shift register).
DMA Mode
In this mode, user code does not move data to and from the UART. DMA request signals going to the external DMA block indicate that
the UART is ready to transmit or receive data. These DMA request signals can be disabled in the COMIEN register.
Example Code to Set Up UART Receive DMA Channel
void UARTRXDMAINIT(void)
{
NVIC_EnableIRQ(DMA_UART_RX_IRQn);
// UArt Tx DMA interrupt enable
pADI_UART->COMLCR = COMLCR_WLS_EIGHTBITS | COMLCR_STOP;
// 8 data bits + 1 stop bit
pADI_UART->COMDIV = 0x41;
// Set UART baud rate
pADI_UART->COMFBR = COMFBR_FBEN_EN | 0x803;
// DIVM = 1, DIVN = 3
pADI_GP1->GPCON = 0x5;
// Configure P1.0/P1.1 for UART
Dma_Init();
pADI_DMA->DMACFG = 0x1;
UARTDMAREAD(uxUARTRXData, 4);
// Enable DMA mode in DMA controller
pADI_DMA->DMAENSET = 0x20;
// Enable UART_RX_DMA Channel
pADI_UART->COMIEN = 0x20;
// Enable DMA Rx transfers
}
void UARTDMAREAD(unsigned char *pucRX_DMA, unsigned int iNumVals)
{
DmaDesc Desc;
// Common configuration of all the descriptors used here
Desc.ctrlCfg.bits.cycle_ctrl = DMA_BASIC;
desc.ctrlcfg.bits.next_useburst = 0x0;
