ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 73 of 196
FLASH CONTROLLER
FLASH CONTROLLER FEATURES
•
256 kB Flash/EE memory in two blocks of 128 kB each (Flash 0 and Flash 1).
•
4 kB information space, which contains factory code.
•
Supports flash block switching for MDIO. For MDIO specific details, see the MDIO section.
FLASH CONTROLLER OVERVIEW
•
Supports read on one flash block and erase/write operation on the other block.
•
Peripheral DMA support for flash keyhole-based write.
•
Kernel present in information space.
•
Supports buffered read, executing code from a 64-bit read while fetching the next 64 bits.
•
32-bit interface for MMR access.
•
Flash program, erase timing controlled via the fixed 16 MHz reference clock.
•
Keyhole open for access, command fail, command complete status bits.
•
Cache provided to speed up execution.
Commands
•
Write command: 64 bits per write.
•
Page erase commands.
•
Mass erase commands for each flash block.
•
Generation of signatures for single or multiple pages.
•
Command abort supported. This is possible by writing to command MMR or by a system interrupt.
•
Keys required for running commands such as a mass erase and the test commands.
Protection, Integrity
•
Write/read protection for user space.
•
Read and write protection for information space.
•
Ability to lock the SW-DP interface.
•
Automatic signature check of information space on reset.
•
User signature check of user space and information space.
•
8-bit ECC
•
1-bit ECC error correction
•
1-bit ECC errors and 2-bit or greater ECC errors can be configured to generate a flash ECC interrupt or a system exception
FLASH CONTROLLER OPERATION
User Space
Flash blocks (Flash 0 and Flash 1) of 128 kB each are available for user code and data. Generally, this can be considered a 256 kB block,
from 0 to 0x3FFFF, except that it is not possible to execute from one flash block while erasing or writing parts of the same block.
The top 24 bytes of user space in each flash block are reserved for a signature, the user write protection pattern, and the user flash failure
analysis key (USERFAAKEY).
If a user tries to read a portion of memory that is not available, a bus error is returned. If a user tries to write via keyhole access to a
portion of memory that is not available, an appropriate error flag is set.
Information Space
Information space of Flash 0 and Flash 1 is located at Address 0x40000 to Address 0x40FFF and is divided up between kernel space, test
space, and calibration space. Information space is reserved for use by Analog Devices. Upon a reset, the hardware forces the part to
execute from the start of information space to copy calibration and configuration values to appropriate MMRs. When the kernel
completes, it passes code execution to the start of user code.
The hardware automatically checks the integrity of the kernel after reset. In the event of a failure, FEESTA[13] is set and user code cannot
run. This bit can only be read via a serial wire read if the serial wire interface is enabled.
