UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 184 of 196
MDIO
MDIO FEATURES
The MDIO interface hardware can receive complete MDIO frames without software intervention. The MDIO interface hardware can also
transmit complete MDIO frames without software intervention as long as the data to be sent is provided before receiving the turnaround
bits (TA) of the read or post read increment address frame. To assist in using and supplying the relevant data, interrupts are generated at
the end of every complete frame. If the PHYADR or DEVADD received does not match the expected values, the frame is not acted upon.
Interrupts can also be generated after every valid PHYADR and DEVADD to permit more sophisticated control within frames.
MDIO OVERVIEW
This MDIO interface is designed for compliance with CFP management interface architecture (as per Draft CFP MSA Management
Interface Specification Version 2.0 r07, June 30, 2011), as shown in Figure 35. This architecture includes an MDIO hardware interface to
handle the serial communications. The transfer of data between this CFP MDIO interface and the MDIO defined memory blocks is done
via software.
HOST MDIO
INTERFACE
(STA)
CFP MDIO
INTERFACE
REGISTERS FOR
REGISTER SET
CFP
IEEE 802.3
CFP MODULE
INTERNAL BUS
NONVOLATILE
MEMORY
(NVM)
DIGITAL
DIAGNOSTIC
MONITORING
(DDM)
MDIO BUS
2
3 OR 5
PORT ADD BUS
(MMD)
CPU/CONTROL LOGIC
1
117
6-
1
34
0x0000
0x8000
0xFFFF
0x7FFF
Figure 35. CFP Management Interface Architecture
MDIO OPERATION
MDIO Frame Structure
The MDIO interface uses the communication data frame structure defined in IEEE 802.3 Clause 45. The frame structure is shown in Figure 36.
Each frame can be either an address frame or a data frame. The total bit length of each frame is 64, consisting of 32 bits preamble, and the
frame command body. The command body consists of six portions, as illustrated in Figure 36. More information about the various frame
types is provided in Table 288. All values are transmitted MSB first.
32-BIT PREAMBLE
ST
OP
PHYADR
DEVADD
TA
16-BIT ADDRESS/DATA
00
ST = START BITS (2 BITS),
OP = OPERATION CODE (2 BITS),
PHYADR = PHYSICAL PORT ADDRESS (5 BITS),
DEVADD = MDIO DEVICE ADDRESS (OR CALLED DEVICE TYPE, 5 BITS),
TA = TURNAROUND BITS (2 BITS),
16-BIT ADDRESS/DATA IS THE PAYLOAD.
OP
00
01
11
10
ACCESS TYPE
ADDRESS
WRITE
READ
POST READ
INCREMENT ADDRESS
ACCESS TYPE
ADDRESS
WRITE
READ
READ INCREMENT
CONTENT
REG ADDRESS
WRITE DATA
READ DATA
READ DATA
DEVADD
00000
00001
00010
00011
DEVICE TYPE
RESERVED
PMA/PMD
WIS
PCS
PHY XS
DTE XS
00100
00101
11
176
-0
35
Figure 36. MDIO Frame Structure
