ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 85 of 196
Bits
Bit Name
Description
Reset Access
00100: WRITE. Use this command to write to flash locations. This command needs a user
key for writing into write protection location and user flash failure analysis key
(USERFAAKEY) location. No key is required for other flash locations. This command takes
the address and data from the FEEADR and FEEFLDATA keyhole registers.
00101: MASSERASE0. Erase all of Flash 0 user space. To enable this operation 0xF123F456
must be written to the FEEKEY register (this is to prevent accidental erases). When the
mass erase has completed, the controller reads every location to verify that all locations
are 0xFFFFFFFFFFFFFFFF. If there is a read verify error, it is indicated in the status register.
00110: MASSERASE1. Erase all of Flash 1 user space. To enable this operation 0xF123F456
must be written to the FEEKEY register (this is to prevent accidental erases). When the
mass erase has completed the controller reads every location to verify that all locations
are 0xFFFFFFFFFFFFFFFF. If there is a read verify error, it is indicated in the status register.
01000: ABORT. If this command is issued, any command currently in progress is stopped.
The status indicates command completed with an error status (FEESTA[5:4] = 0x3). Note
that this is the only command that can be issued while another command is already in
progress. This command can also be used to stop a write that may be in progress. If a
write or erase is aborted, the flash timing is violated and it is not possible to determine if
the write or erase completed successfully. To enable this operation, 0xF123F456 must be
written to the FEEKEY register (this is to prevent accidental aborts).
All other combinations are reserved.
Flash Address Keyhole Register
Address: 0x4001800C, Reset: 0x00000000, Name: FEEFLADR
Table 99. Bit Descriptions for FEEFLADR
Bits
Bit Name
Description
Reset Access
[31:19] RESERVED
Returns 0x0 if read.
0x0
R
[18:3]
FLADDR
Memory mapped address for the flash location. Used to specify flash address for write
command. LSB 3 bits always reads zero.
0x0
RW
[2:0]
RESERVED
Returns 0x0 if read.
0x0
R
Flash Data Register: Keyhole Interface Lower 32 Bits
Address: 0x40018010, Reset: 0x00000000, Name: FEEFLDATA0
Table 100. Bit Descriptions for FEEFLDATA0
Bits
Bit Name
Description
Reset Access
[31:0]
FLDATA0
FLDATA0 forms the lower 32 bits of 64 bit data to be written to flash.
0x0
RW
Flash Data Register: Key-Hole Interface Upper 32 Bits
Address: 0x40018014, Reset: 0x00000000, Name: FEEFLDATA1
Table 101. Bit Descriptions for FEEFLDATA1
Bits
Bit Name
Description
Reset Access
[31:0]
FLDATA1
FLDATA1 forms the upper 32 bits of 64 bit data to be written to flash.
0x0
RW
Lower Page Address Register
Address: 0x40018018, Reset: 0x00000000, Name: FEEADR0
Table 102. Bit Descriptions for FEEADR0
Bits
Bit Name
Description
Reset
Access
[31:19] RESERVED
Return 0 when read.
0x0
RW
[18:11] PAGEADDR0
Used by SIGN and PAGEERASE commands for specifying page address. See the
description of these commands in FEECMD.
0x0
RW
[10:0]
RESERVED
Reserved.
0x0
R
