ADuCM320 Hardware Reference Manual
UG-498
Rev. C | Page 69 of 196
DMA Channel Request Mask Set Register
Address: 0x40010020, Reset: 0x00000000, Name: DMARMSKSET
Table 83. Bit Descriptions for DMARMSKSET
Bits
Bit Name
Description
Reset
Access
[31:14]
RESERVED
Reserved. Reserved, reads back 0.
0x0
R
[13:0]
CHREQMSET
Mask requests from DMA channels. This register disables DMA requests from
peripherals. Each bit of the register represents the corresponding channel number
in the DMA controller.
0x0
RW
Set the appropriate bit to mask the request from the corresponding DMA channel.
Bit 0 corresponds to DMA Channel 0, and Bit M-1 corresponds to DMA Channel M-1.
When read:
Bit [C] = 0, Requests are enabled for Channel C.
Bit [C] = 1, Requests are disabled for Channel C.
When written:
Bit [C] = 0, no effect. Use the DMARMSKCLR register to enable DMA requests.
Bit [C] = 1, disables peripheral associated with Channel C from generating DMA
requests.
DMA Channel Request Mask Clear Register
Address: 0x40010024, Reset: 0x00000000, Name: DMARMSKCLR
Table 84. Bit Descriptions for DMARMSKCLR
Bits
Bit Name
Description
Reset
Access
[31:14]
RESERVED
Reserved.
0x0
R
[13:0]
CHREQMCLR
Clear REQ_MASK_SET bits in DMARMSKSET. This register enables DMA requests
from peripherals by clearing the mask set in DMARMSKSET register. Each bit of
the register represents the corresponding channel number in the DMA
controller.
0x0
W
Set the appropriate bit to clear the corresponding REQ_MASK_SET bit in
DMARMSKSET register.
Bit 0 corresponds to DMA Channel 0, and Bit M-1 corresponds to DMA Channel M-1.
When written:
Bit [C] = 0, no effect. Use the DMARMSKSET register to disable DMA requests.
Bit [C] = 1, enables peripheral associated with Channel C to generate DMA
requests.
DMA Channel Enable Set Register
Address: 0x40010028, Reset: 0x00000000, Name: DMAENSET
Table 85. Bit Descriptions for DMAENSET
Bits
Bit Name
Description
Reset
Access
[31:14]
RESERVED
Reserved.
0x0
R
[13:0]
CHENSET
Enable DMA channels. This register allows for the enabling of DMA channels.
Reading the register returns the enable status of the channels. Each bit of the
register represents the corresponding channel number in the DMA controller.
0x0
RW
Set the appropriate bit to enable the corresponding channel.
Bit 0 corresponds to DMA Channel 0, and Bit M-1 corresponds to DMA Channel M-1.
When read:
Bit [C] = 0, Channel C is disabled.
Bit [C] = 1, Channel C is enabled.
When written:
Bit [C] = 0, no effect. Use the DMAENCLR register to disable the channel.
Bit [C] = 1, enables Channel C.
