UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 84 of 196
Bits
Bit Name
Description
Reset Access
3
WRALMOSTDONE
Write almost complete. Keyhole registers open for access. This bit flags the earliest point
at which the flash controller data and address may be updated for the next command
without affecting an active flash command operation.
0x0
RC
0: cleared to 0 when read
1: set to 1 when a write completes
2
CMDDONE
This bit asserts when a command completes. If there are multiple commands, this status
bit asserts after the first command completes and stays asserted until read.
0x0
RC
0: cleared to 0 when read
1: set to 1 when a command completes
1
WRCLOSE
This bit is asserted when the user has written all keyhole registers for flash write and the
controller has started the write. If this bit is high, all keyhole registers (FEEFLADR,
FEEFLDATA0, FEEFLDATA1) except the command register (FEECMD) are closed for write.
0x0
R
0
CMDBUSY
Command busy. This bit is asserted when the flash block is executing any command
entered via the command register.
0x0
R
Command Control Register: Interrupt Enable Register
Address: 0x40018004, Reset: 0x00000000, Name: FEECON0
Table 97. Bit Descriptions for FEECON0
Bits
Bit Name
Description
Reset Access
[31:3]
RESERVED
Returns 0 when read.
0x0
R
2
IENERR
Command fail interrupt enable. If this bit is set, an interrupt is generated when a
command or flash write completes with an error status.
0x0
RW
0: disable
1: enable
1
IWRALCOMP
Write almost complete interrupt enable. Returns 0 when read.
0x0
RW
0: disable
1: enable
0
IENCMD
Command complete interrupt enable. When set, an interrupt is generated when a
command or flash write completes.
0x0
RW
0: disable
1: enable
Command Register
Address: 0x40018008, Reset: 0x00000000, Name: FEECMD
Table 98. Bit Descriptions for FEECMD
Bits
Bit Name
Description
Reset Access
[31:5]
RESERVED
Returns 0x0. Always returns 0 when read.
0x0
RW
[4:0]
CMD
00000: IDLE. No command executed.
0x0
RW
00001: PAGEERASE. Write the address of the page to be erased to the FEEADR0 register,
then write this code to the FEECMD, and the flash erases the page. When the erase has
completed the flash reads every location in the page to verify all words in the page are
erased. If there is a read verify error, it is indicated in the status register. To erase multiple
pages wait until a previous page erase has completed, check the status, then issue a
command to start the next page erase. Before entering this command, 0xF123F456
must be written to the FEEKEY register.
00010: SIGN. Use this command to generate a signature for a block of data. The
signature is generated on a page by page basis. To generate a signature the address of
the first page of the block is entered in the FEEADR0 register, the address of the last
page is written to the FEEADR1 register, then write this code to the FEECMD register.
When the command has completed the signature is available for reading in the sign
register. The last 4 bytes of the last page in a block is reserved for storing the signature.
Before entering this command 0xF123F456 must be written to the FEEKEY register.
