Analog Devices ADuCM320, Hardware Reference Manual

Page: 120 / 196

UG-498 ADuCM320 Hardware Reference Manual
Rev. C | Page 120 of 196
Bits Bit Name Description Reset Access
2 STXREQ Slave transmit request. If EARLYTXR = 0, STXREQ is set when the direction
bit for a transfer is received high. Thereafter, as long as the transmit FIFO is
not full, this bit remains asserted. Initially, it is asserted on the negative
edge of the SCL pulse that clocks in the direction bit (if the device address
matched also).
0x0 RC
If EARLYTXR = 1, STXREQ is set when the direction bit for a transfer is
received high. Thereafter, as long as the transmit FIFO is not full this bit
remains asserted. Initially, it is asserted after the positive edge of the SCL
pulse that clocks in the direction bit (if the device address matched also).
This bit is cleared on a read of the I2CSSTA register.
1 STXUR Slave transmit FIFO underflow. Is set if a master requests data from the
device, and the Tx FIFO is empty for the rising edge of SCL. 0x0 RC
0 STXFSEREQ Slave Tx FIFO status or early request. If EARLYTXR = 0, this bit is asserted
whenever the slave Tx FIFO is empty. 0x1 RW
If EARLYTXR = 1, TXFSEREQ is set when the direction bit for a transfer is
received high. It asserts on the positive edge of the SCL clock pulse that
clocks in the direction bit (if the device address matched also). It only
asserts once for a transfer. It is cleared when read if EARLYTXR is asserted.
Slave Receive Register
Address: 0x40003430, Reset: 0x0000, Name: I2C1SRX
Table 168. Bit Descriptions for I2C1SRX
Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved 0x0 R
[7:0] I2CSRX Slave receive register 0x0 R
Slave Transmit Register
Address: 0x40003434, Reset: 0x0000, Name: I2C1STX
Table 169. Bit Descriptions for I2C1STX
Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved 0x0 R
[7:0] I2CSTX Slave transmit register 0x0 RW
Hardware General Call ID Register
Address: 0x40003438, Reset: 0x0000, Name: I2C1ALT
Table 170. Bit Descriptions for I2C1ALT
Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
[7:0] ALT Slave Alt. This register is used in conjunction with I2CSCON[3] to match a
master generating a hardware general call. It is used in the case where a
master device cannot be programmed with a slave's address and instead
the slave has to recognize the master's address.
0x0 RW