UG-498
ADuCM320 Hardware Reference Manual
Rev. C | Page 102 of 196
Addressing Modes
7-Bit Addressing
The I2CxID0, I2CxID1, I2CxID2, and I2CxID3 registers contain the slave device IDs. The device compares the four I2CxIDx registers to
the address byte. To be correctly addressed, the seven MSBs of either ID register must be identical to that of the seven MSBs of the first
received address byte. The LSB of the ID registers (the transfer direction bit) is ignored in the process of address recognition.
The master addresses a device using the I2CxADR0 register.
10-Bit Addressing
This feature is enabled by setting I2CxSCON[1] for master and slave mode.
The 10-bit address of the slave is stored in I2CxID0 and I2CxID1, where I2CxID0 contains the first byte of the address, and the R/W bit
and the upper five bits must be programmed to 11110 as shown in Figure 20. I2CxID1 contains the remaining eight bits of the 10-bit
address. I2CxID2 and I2CxID3 can still be programmed with 7-bit addresses.
The master communicates to a 10-bit address slave using the I2CxADR0 and I2CxADR1 registers. The format is described in Figure 20.
To perform a read from a slave with a 10-bit address, the master must first send a 10-bit address with the read/write bit cleared, and then
it must generate a repeated start and send only the first byte of the address with the read/write bit set. A repeated start is generated by
writing to I2CxADR0 while the master is still busy.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
1
1
0
2 MSB
I2CADR0 AND I2CID0
I2CADR1 AND I2CID1
R/W
8 LSB
111
76-
023
Figure 20. 10-Bit Address Format
A repeated start condition occurs when a second start condition is sent to a slave without a stop condition being sent in between. This
allows the master to reverse the direction of the transfer by changing the R/W bit without having to give up control of the bus.
An example of a transfer sequence is shown in Figure 21. This sequence is generally used in cases where the first data sent to the part sets
up the register address to be read from.
MSB
START
BIT
SCL
ACK
BIT
ACK
BIT
SLAVE ADDRESS
SDA
MSB
LSB
LSB
DATA
1
1
7
8
8
9
9
2
3 TO 6
2 TO 7
R/W
MSB
START
BIT
ACK
BIT
ACK
BIT
STOP
BIT
SLAVE ADDRESS
MSB
LSB
LSB
DATA
1
1
7
8
8
9
9
2
3 TO 6
2 TO 7
R/W
1
1
176
-02
4
Figure 21. I
2
C Repeated Start Sequence
On the slave side, an interrupt is generated (if enabled in the I2CxSCON register) when a repeated start and a slave address are received.
This can be differentiated from receiving a start and slave address by using the START and REPSTART status bits in the I2CxSSTA MMR.
On the master side, the master generates a repeated start if the I2CxADR0 register is written while the master is still busy with a
transaction. After the state machine has started to transmit the device address, it is safe to write to the I2CxADR0 register.
For example, if a transaction involving a write, a repeated start, and then a read/write is required, write to the I2CxADR0 register either
after the state machine starts to transmit the device address or after the first MTXREQ interrupt is received. When the transmit FIFO
empties, a repeated start is generated.
Similarly, if a transaction involving a read, a repeated start, and then a read/write is required, write to the first master address byte register,
I2CxADR1, either after the state machine starts to transmit the device address or after the first MRXREQ interrupt is received. When the
requested receive count is reached, a repeated start is generated.
I
2
C Clock Control
The I
2
C peripherals are clocked by a gated 20 MHz system clock (PCLK). The CLKCON5[3] bit must be cleared to enable the clock to the
I
2
C0 block. Similarly, the CLKCON5[4] bit must be cleared to enable the clock to the I
2
C1 block. The CLKCON1[10:8] bits allow the I
2
C
block to be clocked with a slower clock by allowing the 20 MHz clock to be divided, which helps to reduce power.
The I
2
C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode
(400 kHz) or standard mode (100 kHz).
