8-21
Sample Driver
Transmit Initialization
The AIC-6915 provides a set of registers which must be initialized in preparation for
transmitting packets. These registers and the fields which must be initialized in the driver
are summarized below. Register bits which are not explicitly described here may be left at
the default reset value. The developer must determine if these default values need to be
modified for the driver under development. These registers may be initialized in any
order. Refer to Chapter 7 for more detailed information on these registers.
1
T
X
D
ESC
Q
UEUE
C
TRL
(offset 90h): This register provides information about the
Transmit Buffer Descriptor Queue. This includes the descriptor type.
Required Fields:
– SkipLength: The driver may specify a field for software usage at the beginning of
each Transmit Buffer. This length must be a multiple of 8 bytes. The driver may
store any information in this field. It is most useful for storing data provided
when the operating system first initiated the transmit, so that this information
may be referenced when the transmit resources are returned to the operating
system. This field is optional and may be set to zero.
– TxDescQueue64bitAddr = 0: This should be set to 0 for all 32-bit driver
environments.
– TxDescType: This field designates the Transmit Buffer Descriptor Type. Four
choices are available. The operating system environment usually dictates the
choice of descriptor.
2
H
I
P
R
T
X
D
ESC
Q
UEUE
B
ASE
A
DDR
(offset 94h): This register initializes the address of
the high priority Transmit Buffer Descriptor Queue. If only one queue is
implemented, it may be either the low or high priority queue. In this case, there is
no difference between the queues. Note that there is only one Transmit Completion
Descriptor Queue.
Required Fields:
– HighPriorityTxDescQueueBaseAddress: This field contains the high 24 bits of the
buffer address, as allocated from the operating system. If the only queue used is
the low priority queue, this register need not be initialized.
3
L
O
P
R
T
X
D
ESC
Q
UEUE
B
ASE
A
DDR
(offset 98h): This register initializes the address of
the low priority Transmit Buffer Descriptor Queue. In this case, there is no
difference between the queues.
Required Fields:
– LowPriorityTxDescQueuebaseAddress: This field contains the high 24 bits of the
buffer address, as allocated from the operating system. If the only queue used is
the high priority queue, this register need not be initialized.
4
T
X
D
ESC
Q
UEUE
H
IGH
A
DDR
(offset 9Ch): This register contains the high 32 bits of the
Transmit Buffer Descriptor Queue when using 64-bit addressing. It applies to both
the low and high priority queues.
Required Fields:
– T
X
D
ESC
Q
UEUE
H
IGH
A
DDR
= 0: In most operating system environments, this
value is set to zero.
