5-8
AIC-6915 Ethernet LAN Controller Programmer’s Manual
Opcode E
3:0
Return
- Return to main program. When branching from the main
program, the next instruction pointer value of the main program is
saved in a special register. When executing this command, the
information stored in the special register is used as the next
instruction address.
Opcode F
3:0
B
R
O
N
I
NPUT
- When this instruction is executed, the signal
InputBranch
is checked. If the signal is asserted, the branch
address is B
RANCH
A
DD
[7:0]
, otherwise its D
ATA
[7:0].
This
instruction is specifically used to facilitate having a common
program for receive and transmit. On the receive side,
I
NPUT
B
RANCH
is tied to ‘1’. On the receive side, it is tied to ‘0’.
ExcOnClock
4
Instruction is executed or rising edge of clock, otherwise when
D
ATA
V
ALID
is asserted.
ReqNextData
5
Enables the processor to throttle down the incoming data rate.
When asserted, the processor is ready to process the next frame
data.
LoadWR1
6
ALU output is loaded to WR1
LoadWR2
7
ALU output is loaded to WR2
LoadWR3
8
ALU output is loaded to WR3
LoadWR4
9
ALU output is loaded to WR4
LoadLC
10
Loading Loop Counter. The exact data loaded and the counters
operation is defined in Data (I
NST
[47:32]
).
BarrelShifterCtrl
11
‘0’ - Not active (No shift)
‘1’ - Active, shift as specified in Data
MaskCtrl
12
‘0’ - Masking is disabled
‘1’ - AND mask is defined by MaskSel
MaskSel
13
‘0’ - Data[3:1] specifies which nibble of the data is being masked.
D
ATA
[15:4]
specifies the mask.
‘1’ - D
ATA
[14:12]
specifies which nibble of the data is being
masked. D
ATA
[11:0]
specifies the mask.
MuxSelInput2
[16:14]
Controls the 8 input mux operation at ALU input 2.
‘0’ - Data
‘1’ - DataIn (Frame Data)
‘2’ - WR1[15:0]
‘3’ - WR2
‘4’ - WR3
‘5’ - WR4
‘6’ - LC
‘7’ - ReadData
Table 5-2. Instruction Formats (Continued)
Name
Bit Number
Description
