7-17
Register Descriptions
PCI Functional Registers Definition
The following registers are accessible from PCI configuration, memory and direct I/O
space.
PCIDeviceConfig Register
Type: R/W
Internal Registers Subgroup: PCI Functional Registers
Byte Address: 40h - 43h
Table 7-27. PCIDeviceConfig Register
Bit(s)
rw
Reset
Value
Description/Function
31
r/w
0
EnDpeInt:
Enables assertion of DPE (in PCI Configuration Header
Status register) to set PCIInt. PCIInt is an internal interrupt status
bit implemented in InterruptStatus register.
30
r/w
0
EnSseInt:
Enables assertion SSE (in PCI Configuration Header
Status register) to set PCIInt.
29
r/w
0
EnRmaInt:
Enables assertion RMA (in PCI Configuration Header
Status register) to set PCIInt.
28
r/w
0
EnRtaInt:
Enables assertion RTA (in PCI Configuration Header
Status register) to set PCIInt.
27
r/w
0
EnStaInt:
Enables assertion STA (in PCI Configuration Header
Status register) to set PCIInt.
26:25
r
0
Reserved
: Always read as 0.
24
r/w
0
EnDprInt:
Enables assertion DPR (in PCI Configuration Header
Status register) to set PCIInt.
23
r/w
0
IntEnable:
Setting this bit enables the device to assert a PCI
interrupt (PCI_INTA_), else PCI interrupt is disabled. This bit must
be set if the software driver wishes to receive any type of interrupts.
22:20
r/w
0
ExternalRegCsWidth:
Indicates the width of the chip-select when
an access to an external register is performed.
‘000’ - 8 PCI clocks
‘111’ - 7 PCI clocks
‘110’ - 6 PCI clocks
‘101’ - 5 PCI clocks
‘100’ - 4 PCI clocks
‘011’ - 3 PCI clocks
All other combinations are reserved.
19
r/w
0
StopMWrOnCacheLineDis:
When this bit is cleared, the AIC-6915
stops any memory write on a cacheline boundary if the remaining
number of data transfers is more than the cacheline size. A memory
write and invalidate cycle follows. When the bit is set this function is
disabled.
