7-49
Register Descriptions
22:20
r/w
0
RxDmaQueueMode[2:0]:
This field determines how to select the
DMA buffer descriptor queue. The encoding is as follows:
‘000’ - Disable buffer descriptor queue 2. DMA all (good) packets
to buffers taken from queue 1.
‘001’ - DMA all (good) packets to buffers taken from queue 1.
Queue 2 is only used if chosen by the frame processor.
‘010’
- DMA packets whose size is less than or equal to
RxQ2BufferLength
to queue 2. DMA larger packets to queue 1.
The DMA transfer cannot start until at least the number of bytes
equal to RxQ2BufferLength (or the entire packet) are received, or
if the frame processor determines the length of the queue,
whichever occurs sooner.
‘011’
- DMA high-priority packets to queue 2 and standard
priority packets to queue 1.
‘100’
- For IP frames the header frame (Ethernet, IP, TCP/UDP) is
DMA-transferred to DMA queue 1, and the rest of the frame to
DMA queue 2. The frame processor determines where the cutoff
is in the frame. For non-IP frames DMA the frame to queue 2.
Notes
:
1. In all cases, except for ‘000’ mode, the frame processor can
override the selection.
2. If the header-splitting option (RxDmaQueueMode=100b) is
selected, only one receive completion queue can be implemented.
The second queue must remain disabled.
3. If this mode is selected, only one receive completion queue can
be implemented. The second completion queue must remain
disabled.
19
r/w
0
RxUseBackupQueue:
If this bit is set and the DMA queue that
would normally be used to DMA-transfer a packet is out of buffers,
the packet is DMA-transferred to the other queue. This bit is ignored
if R
X
D
MA
Q
UEUE
M
ODE
is 0.
18
r/w
0
RxDmaCrc:
If this bit is cleared, the last 4 bytes of the frame (which
contain the CRC) are not transferred to the host. If the bit is set, the
entire frame transferred. This only affects the final 4 bytes regardless
of ISL mode, so in ISL mode, if the bit is 1, the Ethernet CRC is still
DMA-transferred.
This bit should normally be changed only after a reset (or soft reset)
before the R
X
D
MA
module is enabled. To change it without a reset,
the driver must first disable R
X
D
MA
(by writing to the
G
ENERAL
C
TRL
register), then wait until it reads a 1 from
N
O
B
URST
S
TATE
. The driver can then write R
X
D
MA
C
RC
and re-
enable R
X
D
MA
.
17
r
0
Reserved:
Always written as zero.
16:12
r/w
0
RxEarlyIntThreshold[4:0]:
This field specifies the number of bytes
from the same frame, times 64, DMA-transferred to host memory,
before the E
ARLY
R
ECEIVE
interrupt is generated.
Table 7-62. RxDmaCtrl Register (Continued)
Bit(s)
rw
Reset
Value
Description/Function
