7-50
AIC-6915 Ethernet LAN Controller Programmer’s Manual
RxDescQueue1Ctrl
Type: R/W
Internal Registers Subgroup: Ethernet Functional Registers
Byte Address: D4h - D7h
Note: Many of the bits in R
X
D
ESC
Q
UEUE
1C
TRL
affect descriptor queue 2 as well.
11:8
r/w
6h
RxHighPriorityThreshold[3:0]:
If more than
RxHighPriorityThreshold * 256 ± 128
bytes are in the FIFO,
increase the priority of receive DMA requests. The high-priority
indication is used by the internal arbiter (BAC) to determine which
module (transmit or receive) to service next. The programmable
threshold in bytes is 16 * R
X
H
IGH
P
RIORITY
F
IFO
T
HRESHOLD
.
7
r
0
RxFpTestMode:
If this bit is set the FP is not set between frames.
Used for diagnostic purposes only.
6:0
r/w
4h
RxBurstSize[6:0]:
Specifies the amount of data to write at one time,
times 32 bytes. The receive DMA engine starts a transfer only if
RxBurstSize
of data or the end-of-frame is stored in the FIFO.
If a burst is greater than or equal to a cacheline, and it does not end
on a cache line boundary, the burst size for that burst is rounded
down to end of the previous cacheline. This causes the next burst to
be cache-line aligned.
Table 7-63. RxDescQueue1Ctrl Register
Bit(s)
rw
Reset
Value
Description/Function
31:16
r/w
x
RxQ1BufferLength[15:0]:
Indicates the length of buffer (in bytes) in
descriptor queue 1. This value must be an integral number of 4-byte
words.
15
r/w
0
RxPrefetchDescriptorsMode:
Setting this bit places the AIC-6915 in
Prefetch mode. The AIC-6915 does not wait for the producer to be
updated before fetching a buffer descriptor. When it needs a
descriptor, it always reads the next one. If the Valid bit in the
descriptor is set, the AIC-6915 uses the descriptor. If not, it generates
an R
X
Q1L
OW
B
UFFERS
or R
X
Q2L
OW
B
UFFERS
interrupt, then waits
for the host to place more descriptors in the queue and to write any
value to the producer.
This control bit is used for both descriptor queues.
14
r/w
0
RxDescQ1Entries
- If 0, the receive descriptor queue 1 is 256 entries
maximum. If set, it is 2048 entries maximum.
Table 7-62. RxDmaCtrl Register (Continued)
Bit(s)
rw
Reset
Value
Description/Function
