1-3
Introduction
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Supports 32- and 64-bit addressing of Host DMA buffers and DMA descriptor
queues
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Big/Little endian support for data and descriptors
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Special output pin to indicate high-priority PCI request
Internal Buffer Management
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Large, 8 KByte DMA FIFO (default - 4KByte for transmit, 4-KByte for receive)
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Programmable hardware-controlled transmit FIFO thresholds to prevent underrun
of transmit FIFO and enhance overall system performance
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Unlimited (limited only by the FIFO size) Receive/Transmit frame queueing in the
FIFO to handle long PCI bus latencies
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Hardware support for handling transmit collisions and FIFO underruns without
software intervention
32/64-bit PCI
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Compliant with PCI Local Bus Specification revision 2.1
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Compliant with Intel PCI Bus Power Management Interface Specification Rev 1.00
and Microsoft Device Class Power Management Reference Specification (OnNow)
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PC 97 ready. Implements all hardware features required by Microsoft’s PC 98 design
specification
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Supports 3.3V and 5.0V PCI signaling
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Direct pin out connection to PCI 32/64-bit bus interface
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PCI bus master with zero wait state 32/64-bit memory data transfers at 133/266
MBytes/sec, capable to support leading and trailing byte offset for DMA read and
write (32-bit) for DMA write
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Supports 64-bit addressing in master and target modes
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PCI bus master/slave timing referenced to PCI signal PCLK (33.3 MHz max)
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PCI bus master programmable Latency Timer, Cache Size, And Interrupt Line Select
registers
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Automatically senses if the adapter is plugged into a 32-bit or a 64-bit PCI slot.
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Supports cache line sizes of 16, 32, 64, 128, and 256 bytes
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Supports any combination of active byte enables for all PCI slave accesses
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Supports medium PCI target device-select response time
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Supports, as a bus master, enhanced PCI System memory data read and write
commands:
– Memory Read
– Memory Read Line
– Memory Read Multiple
– Memory Write
