3-3
Transmit Architecture
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When the amount of packet data in the FIFO exceeds the “Transmit Threshold,” or
when the end of packet is already in the FIFO, the “Transmit Frame” state machine
signals the MAC to start transmitting the packet. The transmit frame block handles
reading packets from the FIFO, MAC interface and FIFO link list management. It
also handles “retries” in case collision occurs and handles “aborts” when MAC
signals errors.
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Built-in decode logic in the transmit frame block dynamically adjusts the priority of
BAC arbitration. When the valid data in the FIFO drops below the “High-Priority
Transmit FIFO Threshold” during transmission, the priority of transmit DMA is
asserted and subsequent Transmit DMA operations are allotted a higher priority in
BAC arbitration. Note that this only happens when the Transmit DMA engine and
Transmit Frame are working on the same packet. This algorithm is designed to help
prevent FIFO underrun.
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When the MAC is transmitting a packet, it may encounter network errors such as
late collision, excessive deferral, excess collisions, or long packets. The MAC signals
the transmit frame, which in turn aborts the current transmission. For normal
collisions during the collision window, the MAC signals a “retry” to the Transmit
Frame, which in turn retries transmission of these packets.
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Error handling routines are implemented in the Transmit Frame to retransmit a
packet when transmit FIFO underrun error occurs. The Transmit Frame attempts to
retransmit the packet if the start_of_packet data has not been overwritten by a
subsequent DMA operation. If the Transmit Frame block cannot re-transmit the
packet after three tries, the packet is aborted. The start_of_packet “Producer Index”
of the error packet is DMA-transferred back to the host through the “Completion
Queue”.
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As the MAC completes each packet transmission, it advertises the transmit status of
this packet. The Statistic Block collects both transmit and receive status and stores
them in a local register file. When the mode of “Transmit Complete Interrupt” is on,
the transmit status is DMA-transferred to the host.
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64-bit addressing support on all data buffers. The “Descriptor Queue” and the
“Completion Queue” are also 64-bit addressing, but they share the same high-order
32-bit addresses (same 4-GByte page).
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Power Management Mode defined by PCI Bus Power Management Interface
Specification. When the transmit block is put to the “Sleep” mode, all the state
machines are reset to “Idle” and then the clock is removed.
