4-10
AIC-6915 Ethernet LAN Controller Programmer’s Manual
Table 4-2 lists all 16 PCI commands and the corresponding AIC-6915 response.
Table 4-2. Target Response to PCI Commands
CBE[3:0]_
Command
Abbrev.
AIC-6915 Response to Command
0000
Interrupt
Acknowledge
Ignored
0001
Special Cycle
Ignored
0010
I/O Read
IORD
Supports IORD from the IndirectIoDataPort and
IndirectIoAddress registers. When reading the Data
Port, the AIC-6915 responds (after verifying that the
address matches the assertion of CBE_) in the same
manner as if it has received MRDC with an address
equal to the one stored in IndirectIoAddress.
0011
I/O Write
IOWR
Supports IOWR to the IndirectIoDataPort and
IndirectIoAddress registers. When writing to the
Data port, the AIC-6915 responds (after verifying that
the address matches the assertion of CBE_) in the
same manner as if it has received MWRC with an
address equal to the one stored in IndirectIoAddress.
0100
Reserved
Ignored
0101
Reserved
Ignored
0110
Memory Read
MRDC
Supports MRDC for different combinations of CBE_.
Any unsupported CBE[3:0]_ values result in a target
abort. When no CBE[3:0]_ signal is asserted the data
cycle is treated as a NOP. DEVSEL_ is asserted using
medium speed target response timing. TRDY_ is
asserted as soon as the Target has valid read data. The
period before TRDY_ is asserted will vary depending
on whether the address is internal or external.
0111
Memory Write MWRC
Supports MWRC for different combinations of CBE_.
Any unsupported CBE[3:0]_ values result in a target
abort. When no CBE[3:0]_ signal is asserted the data
cycle is treated as a NOP. DEVSEL_ is asserted using
medium speed target response timing. TRDY_ is
asserted as soon as the target is able to complete (data
is actually written) the cycle and IRDY_ is asserted.
The period before TRDY_ is asserted varies
depending on whether the address is internal or
external.
1000
Reserved
RSVD
Ignored
1001
Reserved
RSVD
Ignored
1010
Configuration
Read
CRDC
Supports CRDC accesses for all registers in single
function Configuration register space. All 32-bits are
always provided without regard for the CBE[3:0]_
value. When no CBE[3:0]_ signals are asserted the
data cycle is treated as a NOP. DEVSEL_ is asserted
using medium speed target response timing.
