4-11
PCI Module Architecture
Configuration Address Space
The AIC-6915, as a single function target, supports type 0 address space accesses with a
single configuration space. As a target, the AIC-6915 uses positive address decoding over
AD[07:02]
along with
CBE[3:0]_
(command is CRDC or CWRC),
IDSEL, AD[01:00] = 0
H
and
FRAME_
to validate the Configuration register address decode. The AIC-6915 then asserts
DEVSEL_
to claim the transaction.
The AIC-6915 supports a read/write operation to its configuration space with any
combination of
CBE[3:0]_
as defined in the PCI specification. For a read, the AIC-6915
always sources all bytes of the addressed register. Reading reserved configuration space
register bytes/bits always return a zero value. Data written to reserved configuration
space register bits or bytes is discarded. No error indication is made for reading or writing
to reserved registers. When more than one Data phase is indicated (burst operation) the
AIC-6915 indicates a disconnect and only accepts the first Data phase.
I/O Address Space (Direct Access)
The AIC-6915 uses Base Address 1 to request an allocation of a 256-byte I/O space block
and supports only read/write operation to the 256-byte registers, including the
IndirectIoDataPort and IndirectIoAddress registers for indirect I/O accesses. When more
than one data phase is indicated (burst operation) the AIC-6915 indicates a disconnect and
only accepts the first data phase.
I/O Address Space (Indirect Access)
Two locations (IndirectIoDataPort, IndirectIoAddress) in I/O space are used as Data and
Address registers. The Address register points to a word location within the 512-K Byte
address space of the AIC-6915. When the AIC-6915 decodes a legal access to its Data
register it selects the address stored in IndirectIoAddress as an input to its address
decoder and performs a read/write cycle using the address in IndirectIoAddress. The
AIC-6915 responds to such a cycle with the exact same behavior as if the master which
initiated the transaction was executing a memory access with the address that is stored in
the IndirectIoAddress register.
1011
Configuration
Write
CWRC
Supports CWRC accesses for all registers in single
function Configuration register space. Any
combination of CBE[3:0]_ values is acceptable for
writing bytes. When no signal is asserted the data
cycle is treated as a NOP. DEVSEL_ is asserted using
medium speed target response timing.
1100
Memory Read
Multiple
MRDMC
Defaults to MRDC
1101
Dual Address
Cycle
DAC
Ignored.
1110
Memory Read
Line
MRDLC
Defaults to MRDC
1111
Memory Write
and Invalidate
MWRIC
Defaults to MWRC
Table 4-2. Target Response to PCI Commands (Continued)
CBE[3:0]_
Command
Abbrev.
AIC-6915 Response to Command
