7-31
Register Descriptions
InterruptStatus Register
Type: R/W
Internal Registers Subgroup: Ethernet Functional Registers
Byte Address: 80h - 83h
This register stores the interrupt vector which indicates the interrupt source. Some of
the bits in the register are cleared on a read, while others must be cleared at the
source. All ‘cleared by read bits’ are also cleared when writing a ‘1’ to the bit. When a
bit in the register is set and the corresponding bit in the I
NTERRUPT
E
N
register is set,
an interrupt is asserted on the PCI bus, assuming that PCI interrupts are enabled in
the PCIDeviceConfig register. Seven interrupt status bits, R
X
Q1D
ONE
I
NT
,
E
ARLY
R
X
Q1I
NT
, R
X
Q2D
ONE
I
NT
, E
ARLY
R
X
Q2I
NT
, T
X
D
MA
D
ONE
I
NT
,
T
X
Q
UEUE
D
ONE
I
NT
and T
X
F
RAME
C
OMPLETE
I
NT
have a second level of masking
using a programmable timer. For more details about the second level masking refer
to T
IMERS
C
ONTROL
register.
Table 7-42. InterruptStatus Register
Bit(s)
rw
Reset
Value
Description/Function
31:28
r/w
0
GPIOInt[3:0]:
This bit is set if the corresponding GPIO bit is
configured to be an input and causes an interrupt. Any GPIO pin
can be configured to be an input and set an interrupt when its high,
or low, or on a change. This bit must be cleared at the source, except
the case where the corresponding GPIO pin is programmed to cause
an interrupt on change. GPIOI
NT
[0]
is also connected to the power
management function and may serve as a wake-up event input.
27
r/w
0
StatisticWrapInt:
Provides an indication of when one of the
statistical counters are going to wrap (change from 7FFFFFFF to
80000000). This bit is cleared on a read, or by writing a ‘1’.
26
r
0
Reserved:
Always reads 0.
25
r
0
AbnormalInterrupt:
Is the logical ‘OR’ of bits [24:16], [7:1].
24
r/w
0
GeneralTimerInt:
Indicates that the G
ENERAL
T
IMER
count reached
its terminal Count of zero. This bit is cleared on a read, or by writing
a ‘1’.
23
r/w
0
SoftInt:
This bit is set when the software driver writes a ‘1’ to the Set
Soft Interrupt bit in the G
ENERAL
C
ONTROL
register. This bit is
cleared by read, or by writing a ‘1’.
22
r/w
0
RxCompletionQueue1Int:
This bit is set if the number of available
entries in Receive Completion Descriptor Queue 1 is below a
programmable threshold. This bit is cleared on a read, or by writing
a ‘1’.
21
r/w
0
TxCompletionQueueInt:
This bit is set if the number of available
entries in the Transmit Completion Descriptor Queue is below a
programmable threshold. This bit is cleared on a read, or by writing
a ‘1’.
20
r
0
PCIInt:
This bit is set when a one of the interrupt status bits in
PCIStatus
register is set and the corresponding enable bit in
PCIConfig
register is also set. This bit must be cleared at the source.
