4-13
PCI Module Architecture
PERR_
The AIC-6915 asserts
PERR_
for detected data parity errors only if
PERRESPEN
is asserted.
As a target device, the AIC-6915 asserts
PERR_
and sets the DPE bit active (
STATUS
register in PCI Configuration header) for write cycles in which it detects a data parity
error, only if it claims the access and asserts
DEVSEL_. PERR_
is asserted for one PCLK
period for each detected error two PCLK periods after the Data phase that contained the
error.
As a master, the AIC-6915 asserts
PERR_
, and sets DPE (PCI header) for read cycles in
which it detects a data parity error. The AIC-6915 asserts
PERR_
only for cycles that it
initiates.
The Command And Byte Enable Bits CBE[3:0]_
The Bus Command and Byte Enable bits are multiplexed on the same PCI pins. During the
address phase of a transaction,
CBE[3:0]_
contain a Bus command that defines the function
to be performed during the transaction. Table 4-3 describes how the AIC-6915 responds to
different commands.
The
CBE[3:0]_
values accepted during a Data phase indicate the valid data bytes. The PCI
target supports any combination of byte enables.
Table 4-3. Address Phase CBE[3:0] Values
CBE [3:0]_
Command
Abbrev.
Type
AIC-6915 Support
Target Master
0000
IAC
Interrupt Acknowledge
No
No
0001
SSC
Special Cycle
No
No
0010
IORDC
I/O Read
Yes
No
0011
IOWRC
I/O Write
Yes
No
0100
RSVD
No
No
0101
RSVD
No
No
0110
MRDC
Memory Read
Yes
Yes
0111
MWRC
Memory Write
Yes
Yes
1000
RSVD
No
No
1001
RSVD
No
No
1010
CRDC
Configuration Read
Yes
No
1011
CWRC
Configuration
Write
Yes No
1100
MRDMC
Memory Read Multiple
1
1
Defaults to Memory Read
Yes
1101
DAC
Dual Address Cycle
No
Yes
1110
MRDLC
Memory Read Line
1
Yes
1111
MWRIC
Memory Write and
Invalidate
2
2
Defaults to Memory Write
Yes
