7-74
AIC-6915 Ethernet LAN Controller Programmer’s Manual
For proper operation, the internal MAC must be reset after enabling any of the
configuration bits in this register by setting bit 15 (M
AC
S
OFT
R
ST
). For example, after
setting the T
X
F
LOW
E
N
and R
X
F
LOW
E
N
bits to enable flow control, set bit 15 to reset the
internal MAC. Setting bit 15 only resets the internal MAC and has no effect on any of the
bits in this register.
BkToBkIPG Register
Type: R/W
Internal Registers Subgroup: MAC Registers
Byte Address: 5008h- 500Bh
2
r/w
0
TxISLEn:
Enables ISL function. When this bit is cleared, regular
Ethernet frames are transmitted and received. When this bit is set
the ISL frame, including the encapsulated Ethernet frame, are
transmitted and received.
1
r/w
0
SimuRst:
This Simulation Reset bit is used for control over internal
random events during simulation, such as placing the random
number generator in a predictable state.
0
r/w
0
TstXmtEn:
This bit is used as internal Early MTXEN signal in
receive module stand-alone test (TestMode bits in MacConfig
register
= 2’b11)
Table 7-93. BkToBkIPG Register
Bit(s)
rw
Reset
Value
Description/Function
31:7
r/w
0
Reserved:
Always read as 0.
6:0
r/w
15h
IPGT:
When doing back-to-back transmit, the inter-packet-gap
(IPG) is enforced by this nibble counter. 0 x 15 is the recommended
value to program into this register in Full duplex operation to meet
minimum IPG requirement. 0 x 11 is the recommended value for
Half duplex operation.
Table 7-92. MacConfig2 Register (Continued)
Bit(s)
rw
Reset
Value
Description/Function
