Adaptec 1737100 - 62044 SGL ENET PCI 4CH Programmer'S Manual Download

Page: 96 / 190

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AIC-6915 Ethernet LAN Controller Programmer’s Manual

PME Event Register

Type: R/W

Internal Registers Subgroup: Ethernet Functional Registers

Byte Address: 58h- 5Bh

Serial EEPROMControlStatus Register

Type: R/W

Internal Registers Subgroup: PCI Functional Registers

Byte Address: 60h - 63h

Table 7-33. PME Event Register

Bit(s)

Reset

Value

Description/Function

31:6

Reserved:

Always read 0.

r/w

ExtPhyReset:

This bit controls the P

ESET

pin directly. Setting

ESET

is the only way to assert the external pin.

LinkFailStatus:

Indicates there is a link fail. This bit is connected

directly to the L

INK

AIL

pin in GPIO bit 0.

r/w

LinkFailEn:

Setting this bit indicates that GPIO bit 0 input mode is

used for a Link Fail event. Clearing the bit disables Link Fail from
generating PME_.

r/w

LinkFailLowActive:

Clearing this bit indicates that GPIO bit 0 is

active high at input mode as a Link Fail indicator. Setting the bit
indicates the GPIO bit 0 is active low.

LinkFailEvt:

Indicates a link fail event. PME_ is asserted. This bit is

cleared when the PME_S

TATUS

bit is cleared.

WakeupEvt:

Indicates a wake-up event from the receive module.

PME_

is asserted. This bit is cleared when PME_S

TATUS

bit is

cleared.

Table 7-34. EEPROMControlStatus Register

Bit(s)

Reset

Value

Description/Function

31:4

Reserved:

Always read as 0.

InitDone

: If the board is set up to read the EEPROM after a hard-

reset, this bit indicates when the initial reading of the EEPROM is
finished. If the board is set up not to read EEPROM after a hard-
reset, this bit is cleared.

Idle

: This is the idle

STATUS

bit indicating the serial EEPROM state

machine is busy or idle.

r/w

WriteEnable:

When this bit is set, it triggers the serial EEPROM

interface to issue a ‘Write Enable’ command. When the command is
completed the bit is cleared.

r/w

WriteDisable

: When this bit is set, it triggers the serial EEPROM

interface to issue a ‘Write Disable’ command. When the command is
completed the bit is cleared.

Summary of Contents for 1737100 - 62044 SGL ENET PCI 4CH

Page 1: ...Document Title ABA 1030 DVB Satellite Receiver Stock Number 512130 00 Rev A Cover 1 Print Spec Number 497767 00 Rev AA Current Date 10 10 98 Programmer s Manual AIC 6915 Ethernet LAN Controller R...

Page 2: ...r 2 Print Spec Number 497767 00 Rev AA Current Date 10 10 98 Adaptec Inc 691 South Milpitas Boulevard Milpitas CA 95035 1998 Adaptec Inc All rights reserved Adaptec and the Adaptec logo are registered...

Page 3: ...ment Title Document Title Stock Number xxxxxx xx Rev x Page Front Matter i Print Spec Number xxxxxx xx Rev x Current Date 10 10 98 ECN Date xx xx xx AIC 6915 Ethernet LAN Controller Programmer s Manua...

Page 4: ...nd information services Electronic Support Technical information including product literature answers to commonly asked questions information on software upgrades and other topics is available electro...

Page 5: ...ive DMA Descriptor Queues 2 2 Normal Mode 2 3 Polling Mode 2 3 32 bit Addressing Mode 2 4 64 bit Addressing Mode 2 4 Completion Status Descriptor Queue 2 4 Accepting frames 2 5 Completion Descriptor 2...

Page 6: ...n ROM Address Space 4 12 Memory Address Space 4 12 Parity 4 12 SERR_ 4 12 PERR_ 4 13 The Command And Byte Enable Bits CBE 3 0 _ 4 13 Illegal Behavior 4 14 5 Frame Processor Architecture Features 5 1 G...

Page 7: ...Registers 7 59 PCI CardBus Registers 7 66 Additional Ethernet Registers 7 69 Ethernet Physical Device Registers 7 69 MAC Control Registers 7 71 Address Filtering Registers 7 82 MAC Statistic Register...

Page 8: ...Transmit Buffer Descriptor Types 8 18 Two Transmit Queues 8 20 Transmit Producer Consumer Model 8 20 Transmit Initialization 8 21 Transmit Handling 8 25 Transmit Completion Interrupt Handling 8 27 AIC...

Page 9: ...xx Rev x Current Date 10 10 98 ECN Date xx xx xx Figure Figures 1 1 AIC 6915 Block Diagram 1 5 2 1 The AIC 6915 Receive Data Structures 2 2 3 1 Transmit Host Communication Data Structure 3 4 4 1 PCI B...

Page 10: ...Document Title Document Title Stock Number xxxxxx xx Rev x Page Front Matter viii Print Spec Number xxxxxx xx Rev x Current Date 10 10 98 ECN Date xx xx xx...

Page 11: ...ntr Bit Functionality 3 7 3 4 Type 1 Transmit DMA Descriptor 32 bit Addressing 3 8 3 5 Type 2 Transmit DMA Descriptor 64 bit Addressing 3 9 3 6 Type 4 Transmit DMA Descriptor 32 bit Addressing only 3...

Page 12: ...nimum Grant Register 7 15 7 26 Maximum Latency Register 7 16 7 27 PCIDeviceConfig Register 7 17 7 28 BacControl Register 7 20 7 29 PCI Monitor1 Register 7 21 7 30 PCI Monitor2 Register 7 22 7 31 Power...

Page 13: ...ess Register 7 53 7 68 RxDescQueue1Ptrs Register 7 53 7 69 RxDescQueue2Ptrs Register 7 54 7 70 RxDmaStatus Register 7 54 7 71 RxAddressFilteringCtrl Register 7 56 7 72 RxFrameTestOut Register 7 58 7 7...

Page 14: ...76 7 99 ReTxCnt Register 7 77 7 100 RandomNumGen Register 7 77 7 101 MskRandomNum Register 7 78 7 102 TotalTxCnt Register 7 78 7 103 RxByteCnt Register 7 79 7 104 TxPauseTimer Register 7 79 7 105 VLA...

Page 15: ...ysical Signaling and PMA Physical Medium Attachment modules The PCI Master uses enhanced data transfer commands to transfer data in zero wait state bursts It supports 32 or 64 bit addressing for host...

Page 16: ...upports Cisco proprietary VLAN ISL frame format Supports IEEE 802 1q VLAN frame format Supports PCI and OnNow power management Supports OnNow wakeup function Calculates TCP IP checksum in transmit mod...

Page 17: ...gement Reference Specification OnNow PC 97 ready Implements all hardware features required by Microsoft s PC 98 design specification Supports 3 3V and 5 0V PCI signaling Direct pin out connection to P...

Page 18: ...generation from hardware firmware and software controlled sources Supports PCI slave accesses to PCI Configuration Header from configuration read write I O indirect read only and memory address space...

Page 19: ...ransmit Receive Data 8 Status Status 32 bits 64 bits PCI Bus 64 bits EPROM Serial Port EPROM DMA Bus 64 bits FIFO Bus 32 bits RxDMA RxFrame TxFrame TxDMA Station Address Data 8 Control Arbiter Sync PC...

Page 20: ...receive as well as the receive descriptor lists RxFrame Manages the current frame being received writing the frame to the FIFO Station Address Compares the address of incoming frames with the stored a...

Page 21: ...available until the end of the packet is DMA transferred Optional 64 bit addressing for buffers and descriptor lists All descriptor lists must be in the same 32 bit region in 64 bit space Buffers can...

Page 22: ...onsumer Index indicates the next entry in the queue to be read If Producer and Consumer indices are equal the queue is empty If Producer 1 mod QueueSize is equal to Consumer then the queue is full The...

Page 23: ...the AIC 6915 needs a descriptor it always reads the next one regardless of the value in the producer pointer If the valid bit is set the AIC 6915 uses the descriptor If not it waits for the host to pl...

Page 24: ...res Producer Consumer type completion queue Programmable queue contains a separate list for receive or the queue can be shared between transmit and receive A second list is available for high priority...

Page 25: ...e AIC 6915 does not report any status when it receives a bad frame but only updates internal statistics Once 64 bytes of a frame have been received successfully the AIC 6915 can start DMA transferring...

Page 26: ...Descriptor 31 24 23 16 15 8 7 0 0 1 Status1 EndIndex Length Status2 VLAN ID Table 2 5 Checksum Type 2 Completion Descriptor 31 24 23 16 15 8 7 0 0 1 Status1 EndIndex Length Status2 Partial TCP UDP Ch...

Page 27: ...y equal to the length of the packet including destination and source addresses type fields etc minus 4 bytes since the CRC isn t transferred by default Setting RxDmaCrc to transfer the CRC can increas...

Page 28: ...ket the checksum was checked and is bad 22 PartialChecksumValid If set the partial checksum is valid 21 Fragmented If set the frame was fragmented 20 TcpFrame If set the frame was a TCP frame 19 UdpFr...

Page 29: ...field 31 16 Partial TCP UDP Checksum When fragmented TCP UDP frames are received the partial TCP UDP checksum of the first frame is calculated by the TCP UDP header and data The partial TCP UDP checks...

Page 30: ......

Page 31: ...it Frame descriptors types 0 3 and 4 can be either fixed size or variable size In fixed size mode the frame size is defined in the MinFrameDescSpacing register regardless of the number of buffer segme...

Page 32: ...he software driver during initialization The transmit DMA module dynamically adjusts DMA burst size so that DMA operations end on cache line boundaries This can improve bus utilization on DMA data tra...

Page 33: ...urrent transmission For normal collisions during the collision window the MAC signals a retry to the Transmit Frame which in turn retries transmission of these packets Error handling routines are impl...

Page 34: ...rs for Lo Priority Packet Data Buffers Completion Queue Status CI Host Memory the AIC 6915 High Priority CI PI Low Priority CI PI Completion Queue Pkt 2 Buf2 Pkt 2 Buf1 Skip Field Frame Header Pkt 1 B...

Page 35: ...nsmit DMA Buffer Descriptor Queues There are two Buffer Descriptor Queues for transmission One for high priority traffic and one for low priority traffic Each Descriptor Queue size has a maximum size...

Page 36: ...follow on segments This field must be nonzero END Indicates that the current descriptor is at the end of the queue The End has different functionality for the following conditions Table 3 1 Type 0 Tr...

Page 37: ...the checksum Table 3 2 End Bit Functionality Desc Type Conditions Functionality Frame 0 3 4 MinFrameDescSpacing 0 The number of bytes between two consecutive frame descriptions is fixed The queue wrap...

Page 38: ...buffer of a frame only The ID Length and Address are valid for all buffers of the frame The software driver must use the End bit only in the first buffer descriptor of a frame The queue wraps around a...

Page 39: ...ta structure given by the upper layer software as a frame descriptor to the descriptor queue area The only difference is the location of Buffer Length and Buffer Address Table 3 5 Type 2 Transmit DMA...

Page 40: ...r the complete DMA transfer of the whole frame from host memory Pri 1 bit Indicates a high or low priority queue Index 15 bits Descriptor Queue Consumer Index points to the beginning of a packet in th...

Page 41: ...o excessive deferral Bit 4 Transmit packet deferred Bit 3 Packet transmitted successfully Bit 2 Transmit field length out of range error Bit 1 Transmit field length check error Bit 0 Transmit CRC erro...

Page 42: ......

Page 43: ...ding and trailing byte offset for DMA read and write 32 bit for DMA write Supports PCI Single Dual address cycles in target mode and Single Dual address cycles in master mode PCI bus master slave timi...

Page 44: ...set is applied INTA_ interrupt generation from hardware firmware and software controlled sources Supports PCI slave accesses to PCI Configuration Header from configuration read write I O indirect read...

Page 45: ...PCI Module BAC Bus Access PCIMST Pcimaster Logic Datapath Logic control logic Address Decoder PCI_PADS PCI_TOP BUFOUTFLOPS OUTFLOPS PCITGT Control Serial EPROM Memory Port Interface EEPROMCNTL BOOTROM...

Page 46: ...he PCI master does not retry transactions that resulted in a master abort no response from target and generates an interrupt to the driver with the RMA Received Master Abort in the PCI Configuration S...

Page 47: ...address alignment DmaAddr 2 0 0 requirement is removed and the AIC 6915 issues a 64 bit transfer for any starting address Upon request from the Ethernet control module for a PCI transfer the PCI maste...

Page 48: ...cks the command to verify that it can respond then asserts DEVSEL_ with medium speed As a target device the AIC 6915 distinguishes between cycles targeted to registers implemented in the PCI clock dom...

Page 49: ...yte memory address space When the target decodes and checks the legality of an access to its Data register it selects the address stored in IndirectIoAddress as an input to its address decoder and per...

Page 50: ...PMCSR register to the D0 state or by a wakeup event that is initiated by the Receive module When the PCI module receives any transfer request from the Receive module it generates a PME_ Power Managem...

Page 51: ...no other PCI slave access can be accepted until the current slave access is completed by the same master for read or the current data has been completed for write The PCI module keeps signalling to th...

Page 52: ...of CBE_ Any unsupported CBE 3 0 _ values result in a target abort When no CBE 3 0 _ signal is asserted the data cycle is treated as a NOP DEVSEL_ is asserted using medium speed target response timing...

Page 53: ...oAddress registers for indirect I O accesses When more than one data phase is indicated burst operation the AIC 6915 indicates a disconnect and only accepts the first data phase I O Address Space Indi...

Page 54: ...while a value of 1h indicates address cache line toggle mode Values 2h and 3h are reserved The AIC 6915 only supports the linear address increment mode As a target device the AIC 6915 allows accesses...

Page 55: ...s During the address phase of a transaction CBE 3 0 _ contain a Bus command that defines the function to be performed during the transaction Table 4 3 describes how the AIC 6915 responds to different...

Page 56: ...of CBE 3 0 _ in an I O cycle does not match the address The AIC 6915 aborts the cycle and sets the ILLEGALBE bit in PCIDEVICESTS register During a memory cycle to the expansion ROM if the address ran...

Page 57: ...gmented TCP frame General Architecture Operation When DATAVALID is asserted a new 16 bit halfword is read by the processor on the rising edge of clock The processor has an option to throttle down the...

Page 58: ...anner Transmit Checksum Accelerator To accelerate the checksum calculation the 25 MHz clock must be connected to the GFP at all times When the GFP is ready to process the frame in a loop it asserts th...

Page 59: ...n All the bits of the Status Control register are available as outputs The GFP is also capable of executing a write instruction using the status data as the write data The 32 bit status registers are...

Page 60: ...icates the receive DMA is requested to interrupt the host immediately after a completion descriptor for current frame is DMA transferred to host memory 21 DmaHeaderOnly If set indicates the receive DM...

Page 61: ...WR3 15 0 Simple ALU Mask Control Adder Comparator ALU Out 31 0 Instruction Loop Counter WR1 WR2 WR3 WR4 LC Input1 Input2 WR1 31 0 WR4 15 0 Flag 8 Input Mux Branch Logic Instruction Ptr LC 15 0 Frame...

Page 62: ...d in the GFP module If the bit is reset the target register is implemented externally Opcode 6 3 0 Read Read location pointed to by the address defined in BRANCHADD 7 0 pass the data through the ALU a...

Page 63: ...registers by executing a Write instruction to address x80 and x81 The first register stores the 2bit Type assigned to each protocol and the second stores the branch address for Type 3 protocol Opcode...

Page 64: ...AVALID is asserted ReqNextData 5 Enables the processor to throttle down the incoming data rate When asserted the processor is ready to process the next frame data LoadWR1 6 ALU output is loaded to WR1...

Page 65: ...Write it indicates the target address Data 47 32 General data 1 field Data is also a control field for the barrel shifter and the Loop Counter If BarrelShifterCtrl 1 then Data 15 If 0 shift right else...

Page 66: ......

Page 67: ...d configuration commands Write operations are limited to configuration commands only Table 6 1 PCI Configuration Header Registers Summary Byte Addr Data Byte 3 Data Byte 2 Data Byte 1 Data byte 0 0000...

Page 68: ...ComplianceTesting For testing PCI Compliance checklist R W 0068 IndirectIoAddress For Accessing indirectly the entire memory address space using PCI I O commands 006C IndirectIoDataPort Ethernet funct...

Page 69: ...pletionPtrs 00D0 RxDmaCtrl Receive DMA control configuration and status registers 00D4 RxDescQueue1Ctrl 00D8 RxDescQueue2Ctrl 00DC RxDescQueueHighAddress 00E0 RxDescQueue1LowAddress 00E4 RxDescQueue2L...

Page 70: ...e only 0108 PciMasterStatus2 010C PciDmaLowHostAddr 0110 BacDmaDiagnostic0 Read only For BAC diagnostic purpose only 0114 BacDmaDiagnostic1 0118 BacDmaDiagnostic2 011C BacDmaDiagnostic3 0120 MacAddr1...

Page 71: ...nst these addresses 6100 617F Hash bitmap The AIC 6915 uses a hash of the destination addresses to index this bitmap Statistic starts offset byte address 0x57000 in memory space 7000 7FFF Ethernet Sta...

Page 72: ......

Page 73: ...ers throughout this section subscribe to the following format Table 7 1 Shade Legends These bits or fields are under software control They may be programmed by software to initialize the controller or...

Page 74: ...bes these subspaces AIC 6915 PCI Address Map Figure 7 1 illustrates the AIC 6915 PCI address map Table 7 2 AIC 6915 PCI Address Space Name Byte Address Range Size bytes Description Reserved 0x70084 0x...

Page 75: ...ional registers 0x0040 0x0100 0x8000 0xA000 MAC registers 0xC000 0xFFFF 0x5000 Rx Frame Processor Instruction memory Tx Frame Processor Instruction memory 0x6000 0x7000 Statistic register file Address...

Page 76: ...d for internal registers 0x50000h Reserved fields are always read as zero Values written to reserved fields are ignored However the host should always write a zero to reserved fields to ensure compati...

Page 77: ...onfiguration Header Byte Address 00h 01h PCI DeviceID Register Type R Internal Registers Subgroup PCI Configuration Header Byte Address 02h 03h Table 7 3 PCI Vendor ID Register Bit s rw Reset Value De...

Page 78: ...read commands PERRESPEN is set inactive during and after assertion of PCI_PCIRST_ 5 r 0 VSNOOPEN VGA Snoop Enable Always reads 0 The AIC 6915 does not support VSNOOPEN 4 r w 0 MWRICEN Memory Write and...

Page 79: ...a target during an Address phase or a Write Data phase and by the transaction master during a Read Data phase DPE is set inactive during and after assertion of PCI_PCIRST_ or by a write to the STATUS...

Page 80: ...0 1h 8 r w 0 DPR Data Parity Reported Setting this bit indicates that the master of a transaction with it s PERRESPEN bit set has either detected PCI_PERR_ asserted or asserted PCI_PERR_ DPR is clear...

Page 81: ...l of a PCI device Device Revision values change in metal only Table 7 8 Program Interface Register Bit s rw Reset Value Description Function 7 0 r 00h PROGINFC 7 0 The Program Interface register value...

Page 82: ...ss 0Dh Table 7 10 BaseClass Register Bit s rw Reset value Description Function 7 0 r 02h BASECLASS 7 0 The BaseClass register identifies which base class the PCI device has been assigned to The BASECL...

Page 83: ...IC 6915 is a single function device 6 0 r 0 HDRTYPE 6 0 Always read 0 Table 7 14 BIST Register Bit s rw Reset Value Description Function 7 0 r 0 BIST 7 0 Always read as 0 Table 7 15 Base Address 0 Reg...

Page 84: ...the card information structure begins The pointer is used in a CardBus PC card environment The value of this register is loaded from the external serial EPROM after a PCI hard reset Table 7 16 High B...

Page 85: ...9004h SubSystemVendorID 15 0 The PCI SubSystem Vendor Identifier register helps to identify the vendor of the add in board even though the PCI controller has been designed by another vendor and has an...

Page 86: ...External ROM Enable When this bit is set along with the MSPACEEN bit in the Configuration Command register this bit enables the device to accept accesses to expansion ROM Unless both EXROMEN and MSPAC...

Page 87: ...deasserted This feature enables the integration of multiple AIC 6915 devices on the same PCI card as a multiport Ethernet NIC and treats the card as one PCI device with multiple functions having diff...

Page 88: ...riod of time in units of 0 25 microseconds Assuming an average required transfer rate of 30MByte Sec 25M 5M overhead and an average burst size of 64 bytes which takes 0 48usec based on clock of 33MHz...

Page 89: ...ster to set PCIInt 27 r w 0 EnStaInt Enables assertion STA in PCI Configuration Header Status register to set PCIInt 26 25 r 0 Reserved Always read as 0 24 r w 0 EnDprInt Enables assertion DPR in PCI...

Page 90: ...e software must make sure that PCIMSTDMAEN is set MASTEREN is set PCI Command register ISPACEEN or MSPACEEN is set PCI Command register 12 r w 0 StopOnCachelineEn When set the AIC 6915 stops any memor...

Page 91: ...changed Note The address is incremented only if the PCI cycle is completed successfully 3 r w 0 Reserved Always read as 0 2 r 0 System64 This bit indicates the system bus size Setting the bit indicat...

Page 92: ...ndian format Note This bit has no affect on the way descriptors are read from and written to host memory 3 r w 0 SingleDmaMode Is used for debugging only In this mode the BAC resets its BacDmaEn bit a...

Page 93: ...and HostAddress TransferSize 4 GByte 2 BAC receives DMA write request and Host address is not on word boundary or Transfer Size is not 4 word aligned 3 A DMA transfer is completed and the BAC is oper...

Page 94: ...rted The count is presented in 1unit 64cycles This field is reset to zero if PCIMASTERBUSUTILIZATION wraps around to 0 Table 7 31 Power Management Register Bit s rw Reset Value Description Function 31...

Page 95: ...es not provide information about the power it consumes 23 16 r 0 Reserved Always read as 0 15 r w 0 PmeStatus This bit is set when the function would normally assert the PME_ signal independent of the...

Page 96: ...Link Fail indicator Setting the bit indicates the GPIO bit 0 is active low 1 r 0 LinkFailEvt Indicates a link fail event PME_ is asserted This bit is cleared when the PME_STATUS bit is cleared 0 r 0...

Page 97: ...2011 TX Rev 1 10 62022 28 62044 20 62020 FX 28 69011 TX 9 SubSystem Device ID 15 8 00 10 Interrupt Pin 7 0 01 11 Card Bus 7 0 00 12 Card Bus 15 8 00 13 Card Bus 23 16 00 14 Card Bus 31 24 00 15 MAC ad...

Page 98: ...Table 7 37 IndirectIoAddress Register Bit s rw Reset Value Description Function 31 19 r 0 Reserved 18 2 r w 0 IndirectIoAddress Points to a word 4 byte location in the AIC 6915 512 KByte address space...

Page 99: ...module data buffer descriptors completion descriptors does not issue any DMA requests The bit is cleared by the software driver or when the PCI master encounters a PCI error which should disable the...

Page 100: ...GeneralTimer that controls the spacing of GeneralTimerInt When the bit is cleared the timer has a resolution of 24 TimerClock periods 12 8 s When the bit is set the resolution is 29 TimerClock period...

Page 101: ...and completing the DMA transfer of a small frame then RXDONEINT by passes the masking timer and asserts the external PCI interrupt line When SMALLFRAMEBYPASS is reset the AIC 6915 treats all received...

Page 102: ...EINT from causing a PCI interrupt for a period defined by IntMaskPeriod The number loaded to the timer is IntMaskPeriod 128 The following samples of masking periods are calculated based on TimerClockP...

Page 103: ...pt the case where the corresponding GPIO pin is programmed to cause an interrupt on change GPIOINT 0 is also connected to the power management function and may serve as a wake up event input 27 r w 0...

Page 104: ...e 15 r 0 NormalInterrupt Is the logical OR of bits 8 9 10 11 12 13 14 14 r w 0 TxFrameCompleteInt Indicates that at least one complete Ethernet frame has been transmitted out of the AIC 6915 The AIC 6...

Page 105: ...a buffer descriptor and the number of buffers available in the queue is less than a programmable threshold as defined in the RxDmaCtrl register This bit is cleared on a read or by writing a 1 The num...

Page 106: ...Function 31 28 r 0 GPIOInt 27 r 0 StatisticWrapInt 26 r 0 Reserved 25 r 0 AbNormalInterrupt 24 r 0 GeneralTimerInt 23 r 0 SoftInt 22 r 0 RxCompletionQueue1Int 21 r 0 TxCompletionQueueInt 20 r 0 PCIInt...

Page 107: ...Reserved 25 r w 0 AbNormalInterruptEn 24 r w 0 GeneralTimerIntEn 23 r w 0 SoftIntEn 22 r w 0 RxCompletionQueue1IntEn 21 r w 0 TxCompletionQueueIntEn 20 r w 0 PCIIntEn 19 r w 0 DmaErrIntEn 18 r w 0 Tx...

Page 108: ...ng GPIO pin is configured as an output Bit 0 controls GPIO 0 bit 1 controls GPIO 1 etc 0 Regular output 1 Open Drain output 15 8 r w 0 GPIOInpMode 7 0 Active only when the corresponding GPIO pin is co...

Page 109: ...d Always written as 0 20 16 r w 0 SkipLength At the front of every frame buffer transmit DMA descriptor there is a field reserved for software driver usage The skip length field specifies that field s...

Page 110: ...limited 3 r w 0 DisableTxDmaCompletion If this bit is set the AIC 6915 does not transfer completion descriptors and does not set the interrupt status bit TXDMADONEINT If the bit is cleared default st...

Page 111: ...iver during device initialization The address must be aligned to a 256 byte boundary The producer and consumer indices are pointing to a doubleword 8 byte address in the queue 7 0 r w 0 HighPriorityTx...

Page 112: ...le 7 50 TxDescQueueProducerIndex Register Bit s rw Reset Value Description Function 31 27 r 0 Reserved Always read as 0 26 16 r w 0 HiPrTxProducerIndex Written by the software driver and read by the A...

Page 113: ...tor The producer and consumer indices point to a doubleword 8 byte address in the queue 15 11 r 0 Reserved Always reads 0 10 0 r 0 LoPrTxConsumerIndex Written by the AIC 6915 and read by the software...

Page 114: ...to the FIFO Table 7 54 TransmitFrameControlStatus Register Bit s rw Reset Value Description Function 31 25 r 0 Mac TX Interface Interface signals between the MAC and TX blocks These bits are Start of...

Page 115: ...host memory allocated for the completion queue is either 4 KBytes 8 KBytes or 16 KBytes programmable by bits 5 4 RXCOMPLETIONQ1TYPE The start address must be aligned to a 256 byte boundary The total...

Page 116: ...s field contains the starting address of the queue in host memory It is written by the host driver during initialization and read by the AIC 6915 The amount of host memory allocated for the completion...

Page 117: ...s bit indicates if Receive Completion queue 1 is located in 64 bit address space If so the AIC 6915 PCI Master must use 64 bit addressing mode to access the queue 6 r w 0 RxCompletionQ2ProducerWe When...

Page 118: ...le threshold When the bit is set the interrupt status bit is asserted if the number of valid completion descriptors in the queue is greater than or equal to the programmable threshold 30 26 r 0 Reserv...

Page 119: ...ompletion descriptor is successfully DMA transferred to the receive completion list in host memory The software driver can write this field only if RxCompletionProducerWe is set which also disables th...

Page 120: ...module it actually affects the operation of receive frames 29 r w 0 RxDmaBadFrames If set accept frames with dribble nibble code violation or cut off due to FIFO overflow Otherwise they are rejected 2...

Page 121: ...ceive completion queue can be implemented The second queue must remain disabled 3 If this mode is selected only one receive completion queue can be implemented The second completion queue must remain...

Page 122: ...line and it does not end on a cache line boundary the burst size for that burst is rounded down to end of the previous cacheline This causes the next burst to be cache line aligned Table 7 63 RxDescQu...

Page 123: ...is used for both descriptor queues 10 8 r w 0 RxDescSpacing 2 0 Specifies the minimum offset between descriptors If the size of the descriptor is larger than the DescriptorSpacing the spacing between...

Page 124: ...erved Always written with zero 7 0 r w 0 RxQ2MinDescriptorsThreshold 7 0 If the number of receive buffers available producer consumer is less than RxQ2MinDescriptorsThreshold then the AIC 6915 generat...

Page 125: ...ways write 0 Table 7 68 RxDescQueue1Ptrs Register Bit s rw Reset Value Description Function 31 27 r w 0 Reserved Always write zero 26 16 r w RxDescQ1Consumer Written by the AIC 6915 and read by host T...

Page 126: ...me to reuse the buffers Software can write this field only after setting the RXQ2CONSUMERWE bit in the RXDESCQUEUE2CTRL register 15 11 r w 0 Reserved Always write 0 10 0 r w 0 RxDescQ2Producer Written...

Page 127: ...se with a matching programmed address Refer to the PERFECTFILTERINGMODE field for more information 2 Hash Address Match The internal CRC computation logic in the AIC 6915 is executed on each byte of t...

Page 128: ...eptBroadcast When set all incoming packets with a multicast address except broadcast packets are received and DMA transferred regardless of the destination address If VLANMODE is set and the frame is...

Page 129: ...ardless of VLAN 3 r w 0 HashPriorityEnable If this bit is set the hash priority table is used to determine the priority of frames that are accepted because of their hash address matching Note If a fra...

Page 130: ...0 1 TestRxFrame status1 else If TestSel 2 0 2 TestRxFrame status2 else If TestSel 2 0 3 TestRxFrame status3 where status0 main_ready Main End bypass_fp receive_byte hword_next byte_state status1 2 b0...

Page 131: ...t is set by hardware when the PCI target detects a memory access to an address that is mapped to both the Expansion ROM space and the memory space The bit is cleared by writing a 1 2 r w 0 IllegalWrit...

Page 132: ...ion was to 64 bit address space 15 r 0 DmaRead When set this bit indicates that the DMA operation is DMA read otherwise it is a DMA write 14 r 1 PCIMstDmaDone When set this bit indicates that the PCI...

Page 133: ...unt register contains a count of the number of words to be transferred between system memory and the PCI bus when the PCI is an active bus master HCNT decrements by one each time a word is transferred...

Page 134: ...when the AIC 6915 is an active bus master The PCITransferCount field functions as a counter that decrements by one each time a byte is transferred between the PCI master and the FIFOs Transfers are i...

Page 135: ...BacDmaDiagnostic2 Register Bit s rw Reset Value Description Function 31 29 r 0 Reserved Always read as 0 28 16 r 1X EtherFifoPtr 12 0 Indicates the byte address of the current DMA requester FIFO point...

Page 136: ...Is the third highest priority DMA request line and is connected to the transmit completion descriptor request line 19 r 0 RxDescReq Is the second highest priority DMA request line and is connected to...

Page 137: ...dr1 Register Bit s rw Reset Value Description Function 31 0 r w 0 MacAddr 31 0 The MAC address of the AIC 6915 is read from the external serial EPROM and loaded in to the MACADDR register The software...

Page 138: ...cation indicates that all bits except bit 15 should be set when the corresponding bit in the Function Present State register changes state Since none of those bits can change state the bits in the Fun...

Page 139: ...it 15 INTR of the FUNCTIONEVENT register is set an interrupt is generated 14 5 r 0 Reserved Always reads 0 4 r 0 GWake Always reads 0 3 2 r 0 BVD 2 1 Always reads 0 1 r 0 Ready Always reads 0 0 r 0 WP...

Page 140: ...terrupt function is supported only bit 15 is implemented Table 7 86 ForceFunction Register Bit s rw Reset Value Description Function 31 16 r 0 Reserved Always reads 0 15 r w 0 Intr Setting this bit al...

Page 141: ...register 29 16 r 0 Reserved Always read as 0 15 0 r w 0 MiiRegDataPort The Data port is used for accessing MII registers implemented in external physical device s The Data port resides in a 4 KBytes...

Page 142: ...M Test Select This bit is used by the Boot EPROM control block to multiplex out test output bits instead of using regular functional output bits This bit must be set for the test mode to be active 7 4...

Page 143: ...flow control frame is taken from TXPAUSETIMER register 10 r w 0 RxFlowEn Receive flow control enable When this bit is cleared pause frames are treated as other control frames When the bit is set paus...

Page 144: ...immediately after SFD 3 r w 0 TxHalfDuplexJam If software sets this bit when the AIC 6915 is in half duplex mode and the receive is active Carrier Sense active the AIC 6915 starts transmitting to crea...

Page 145: ...ackOff When this bit is reset the Transmit Half Duplex Flow Control bit in the configuration register is ignored When this bit is set the transmit engine optionally asserts back pressure with or witho...

Page 146: ...luding the encapsulated Ethernet frame are transmitted and received 1 r w 0 SimuRst This Simulation Reset bit is used for control over internal random events during simulation such as placing the rand...

Page 147: ...expires the transmit engine continues to count time even though a carrier has been sensed When IPGR2 expires the transmit engine transmits the data and thus forces a collision on the network If some...

Page 148: ...d unless the HUGEENABLE control bit in the configuration is asserted in which case no transmit frame length is enforced Table 7 97 TxNibbleCnt Register Bit s rw Reset Value Description Function 31 16...

Page 149: ...ck of the number of times a retransmission has occurred The final count is loaded in statistics vectors It should only be written for test purposes such as speeding up simulation time Table 7 100 Rand...

Page 150: ...example only the LSB of RandomNumGen is evaluated to determine the number of slot times of delay before the first retransmission It may be either 0 or 1 Only the 2 least significant bits of RANDOMNUM...

Page 151: ...a multipurpose counter used internally to count the number of bytes at different times It should only be written for test purposes such as testing huge frame functionality Table 7 104 TxPauseTimer Re...

Page 152: ...nal MII PHY register specified by MIIPHYAD and MIIREGAD in the MIIAdr register The MIIADR register must be appropriately set before turning on this bit The intention use of this bit is to continuously...

Page 153: ...Address PHY 0 2000h PHY 1 2080h PHY 2 2100h PHY 3 2180h PHY 4 2200h PHY 5 2280h PHY 6 2300h PHY 7 2380h PHY 8 2400h PHY 9 2480h PHY 10 2500h PHY 11 2580h PHY 12 2600h PHY 13 2680h PHY 14 2700h PHY 15...

Page 154: ...Bytes0 1 Bytes2 3 Bytes4 5 10 4 2 Bytes0 1 Bytes2 3 Bytes4 5 20 8 3 Bytes0 1 Bytes2 3 Bytes4 5 30 C 4 Bytes0 1 Bytes2 3 Bytes4 5 40 10 5 Bytes0 1 Bytes2 3 Bytes4 5 50 14 6 Bytes0 1 Bytes2 3 Bytes4 5 6...

Page 155: ...optionally be used to hash only multicast frames or any frames When hashing multicast frames the VLAN address of VLAN frames can also be verified before accepting a frame Hash Priorities An additiona...

Page 156: ...Ch Transmit CRC Errors MAC TX M 32 Transmit frame with error in CRC field 10h Transmit OK Octets MAC TX R 32 Count the number of octets of successfully transmitted frames 14h Transmit Deferred Frames...

Page 157: ...h Control Frames Received with unsupported opcode MAC RX R 32 Count the number of Control frames successfully received but with unsupported opcode 54h Receive Frames Too Long MAC RX RMON 32 Count the...

Page 158: ...ber of receive frames whose length is between 512 and 1023 bytes 78h Receive Packets 1024 to 1518 Bytes MAC RX RMON 32 Count the number of receive frames whose length is between 1024 and 1518 bytes 7C...

Page 159: ...sor Register Bit s rw Reset Value Description Function 31 0 r w x TxGfpMem This field defines a 256 byte address space that the software driver can use to access the transmit General Frame Processor p...

Page 160: ......

Page 161: ...n utilize several C macros to demonstrate driver initialization of the AIC 6915 The actual implementation of these macros is operating system specific These macros include the following AIC6915_READ_R...

Page 162: ...dresses in the Receive DMA Descriptors Queue After an Ethernet packet has been received from the network the AIC 6915 Consumes a receive buffer by dequeueing it from the Receive DMA Descriptors Queue...

Page 163: ...receive descriptors These structures all reside in host memory Memory allocation is unique to each operating system and will not be covered here in detail For an example under Windows NT refer to the...

Page 164: ...to specify PCI interrupts At a minimum the INTENABLE bit must be set A two microsecond delay is required after this register is set 6 PCI Status Register offset 06h The PCI Status register must be cl...

Page 165: ...ndows NT driver example of driver reset The board has already been discovered Reset the PHY InitAutonegotiate Initialize GeneralEthernetCtrl register to stop any DMA activity AIC6915_WRITE_REG Adapter...

Page 166: ...REG Adapter RegisterBaseVa BacControl BacControlValue Clear all interrupts that are cleared on read Other interrupts must be cleared at the source AIC6915_READ_REG Adapter RegisterBaseVa InterruptStat...

Page 167: ...ose to implement two receive completion queues if the protocol environment can utilize packet sorting based on priority or size The AIC 6915 controller offers the choices of sorting based on address f...

Page 168: ...scriptor Queue is fixed at either 256 or 2048 This number of entries is programmed using the RXDESCQ1ENTRIES bit in the RXDESCQUEUE1CTRL register The receive buffer descriptor contains the physical ad...

Page 169: ...nsumer of Receive Buffer Descriptors as it uses the buffer resources provided by the driver The AIC 6915 writes entries to the Receive Completion Descriptor Queue and is therefore the producer of Rece...

Page 170: ...ueue consumer indices Required Fields RxCompletionQ1ConsumerIndex 0 Initialize the Receive Completion Descriptor Queue 1 consumer index to zero TxCompletionConsumerIndex 0 Initialize the Transmit Comp...

Page 171: ...er Descriptor Queue 8 RXDESCQUEUE2CTRL offset D8h This register defines Receive Buffer Descriptor Queue 2 It is required only if two Receive Buffer Descriptor Queues are used Required Fields RxQ2Buffe...

Page 172: ...r consumer model initialize the producer index to zero to indicate that the queue is empty For the polling model initialize the producer index to any value The Valid bit in the Receive Buffer descript...

Page 173: ...onsumer model RxDescQueue1CtrlValue RxQ1MinDescThreshold Adapter RxQ1MinDescThreshold do not allow software to write consumer index RxDescQueue1CtrlValue RxQ1ConsumerWe 0 no spacing between descriptor...

Page 174: ...ucer and Consumer indices to 0 NOTE we re using polling model on the receive side AIC6915_WRITE_REG RxDescQueue1Ptrs 0 Use default value for RxDescQueue2Ptrs Initialize RxAddressFilteringCtrl read cur...

Page 175: ...ws NT example Receive Interrupt Handling Pseudocode This example is for the polling model Illustrates the use of a single Receive Completion Queue and Receive Buffer Queue Process the receive interrup...

Page 176: ...valid Adapter RxDesc Adapter RxDescQProducerIndex Valid 1 Adapter RxDescQProducerIndex RxDescIndex We re done with receives Transmit Process The transmit process in the AIC 6915 utilizes the producer...

Page 177: ...which is an address index must be converted to a software index before the driver uses it to retrieve the Transmit Buffer Descriptor The address index is incremented by the size of the Transmit Buffer...

Page 178: ...to 000b An optional skip field is available for use by the driver for storage of pertinent information The skip field size must be a multiple of 8 bytes Since this descriptor type is a frame descripto...

Page 179: ...MA Buffer Descriptor Queue section in the Transmit Architecture chapter for a description of all fields in this descriptor type Type 3 descriptor This descriptor type is reserved and is currently not...

Page 180: ...ransmit buffers and is responsible for maintaining the Transmit Buffer Descriptor consumer index The AIC 6915 generates a Transmit Done or Transmit DMA interrupt and provides information in the Transm...

Page 181: ...scType This field designates the Transmit Buffer Descriptor Type Four choices are available The operating system environment usually dictates the choice of descriptor 2 HIPRTXDESCQUEUEBASEADDR offset...

Page 182: ...and therefore is dependent upon the type of descriptor Required Fields HiPrTxConsumerIndex 0 The consumer index should be initialized to zero which is the reset value LoPrTxConsumerIndex 0 The consume...

Page 183: ...d only if two receive completion queues are implemented In this case RxCompletionQ2ConsumerIndex should be initialized to zero Example Windows NT driver example Single Transmit Completion and Buffer D...

Page 184: ...ansmitThreshold from registry AIC6915_WRITE_REG TxFrameCtrl TxFrameCtrlValue Set up the TxCompletionQueueCtrl register TxCompletionQCtrlValue TxCompletionQThreshold Adapter TxCompletionQThreshold from...

Page 185: ...riptor queue in units of 8 bytes In this example we are using Type 1 descriptors with an 8 byte skip field The descriptor size is therefore 16 bytes In units of 8 bytes each descriptor is indexed by 2...

Page 186: ...he Reserved field save the address of the originating packet This will be used later when we process the Transmit Complete interrupt TxDesc Reserved OwningPacket Packet FirstBuffer FALSE Remember wher...

Page 187: ...that packet in the Transmit Completion Descriptor Queue and initiates a TXFRAMECOMPLETE interrupt or a TXDMADONE interrupt The driver must process this interrupt and return the transmitted packet reso...

Page 188: ...stored in the skip field at that time NdisMSendComplete Adapter MiniportAdapterHandle TxDesc Reserved OwningPacket NDIS_STATUS_SUCCESS TxComQConsumerIndex TxComQConsumerIndex AIC6915_NUMBER_OF_TX_COM...

Page 189: ...criptor Queues Option to implement one or two queues Set through define in A6915HRD H Size of Rx Buffer Descriptor Queue Option to 256 or 2048 entry receive buffer Set through define in A6915HRD H Ski...

Page 190: ...driver and an NDIS 5 0 driver in the DDK They were developed using Version 5 0 of the Microsoft Visual C compiler When using this compiler version the Ox optimization cannot be used in a free build U...

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