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AIC-6915 Ethernet LAN Controller Programmer’s Manual
Expansion ROM Address Space
When in target mode, the AIC-6915 allows access to an 8-bit ROM/EEPROM (connected
to the External Memory Interface port) through the expansion ROM address space. The
AIC-6915 uses positive address decoding over
EXROMCTL
register (stored value),
AD[31:02], CBE[3:0]_
(command) and
FRAME_
to obtain the doubleword access decode and
claim the transaction by asserting (
DEVSEL_
= medium speed).
For memory read from the expansion ROM space, the memory interface module of the
AIC-6915 performs a burst of four consecutive read accesses from the ROM, incrementing
automatically the address with values of 0, 1, 2, and 3 to assemble a 32-bit value. Usually
this kind of transfer takes longer than 16 PCI clocks, so the memory interface requests the
PCI target to retry the cycle. The transfer is completed only when all the data is available
and ready in the memory interface module. The AIC-6915 does not support writes to
expansion ROM space.
Memory Address Space
The AIC-6915 uses Base Address 0 to request an allocation of a 512-KBytes memory space
block.
AD[01:00]
are excluded from the address decode and defaults to a word-aligned address.
The value on
AD[01:00]
are used in the memory address space to indicate different
memory address transfer modes. A value of 0h indicates linear address increment mode,
while a value of 1h indicates address cache line toggle mode. Values 2h and 3h are
reserved. The AIC-6915 only supports the linear address increment mode.
As a target device, the AIC-6915 allows accesses to it's 512-KByte allocated memory space.
The AIC-6915 uses positive address decoding over
BASEADR0
register (stored value),
AD[31:02], CBE[3:0]_
(command) and
FRAME_
to obtain the doubleword access decode,
then claims the transaction by asserting (
DEVSEL_
= medium speed). The AIC-6915 uses
the
CBE[3:0]_
(data) value to complete the decode.
Parity
The AIC-6915 implements even parity that protects both the
AD[31:00]
and C
BE[3:0]_
busses.
PAR
is generated by the agent that is sourcing the 32-bit address of the transaction
and/or the data of the transaction and includes the
CBE[3:0]
values even if not sourcing
them. The state of
PAR
is valid for the value on
AD[31:00]
and
CBE[3:0]
during the previous
PCLK period, excluding turn-around cycles of
AD[31:00]
(for which the
PAR
is invalid).
SERR_
The AIC-6915 asserts
SERR_
when it detects an address parity error only if the
PERRESPEN
(Parity Error Response Enable,
COMMAND
register in PCI Configuration
header) and
SERRESPEN
(System Error Response Enable,
COMMAND
register in PCI
Configuration header) bits are set.
SERR_
is restored only by a weak pull-up on the system
board, and may take several PCLK periods to recover to a deasserted state.
SERR_
is
asserted for one PCLK period on an address errors.
SERR_
is asserted two PCLK periods
after the Address phase that contained the error. The AIC-6915 as a master does not
monitor or assert
SERR
.
