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Receive Architecture
Features
The host-related Receive Architecture features are
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Interrupts may be delayed so that only one interrupt is generated when a group of
frames is received
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Choice of shared or separate completion lists for receive and transmit. An optional
second completion list can be used for high-priority traffic
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Two programmable 256-entry or 2048-entry buffer descriptor lists, with optional
smaller lists as defined by an “end” bit
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All receive buffers can be either the same size, or have individual sizes
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Early receive interrupt is generated when the DMA-transfer of a programmable
number of bytes is complete. Status is not available until the end of the packet is
DMA-transferred
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Optional 64-bit addressing for buffers and descriptor lists. All descriptor lists must
be in the same 32-bit region in 64-bit space. Buffers can be located anywhere within
the space, but an individual buffer must not cross a 4-GByte boundary
The internal Receive Architecture features are
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4K Byte receive FIFO (The actual 8KByte on-chip SRAM is shared with Transmit)
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The FIFO does not have an arbitrary limit on the number of frames, but can continue
receiving frames until it is full, regardless of the frame sizes
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Each frame requires only 8 bytes of overhead in the FIFO
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IEEE 802.3x based flow control
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Cisco’s ISL frame support (Implemented in the MAC)
Additional value-added features
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Power management.
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Wakeup frames compliant to Microsoft’s OnNow specification
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TCP and UDP checksum support
