7-29
Register Descriptions
12
r/w
0
RxHiPrBypass:
If this bit is set, bypass the interrupt masking timer
when generating RxDoneInt after DMA-transferring the
completion descriptor of a high-priority frame.
11
r/w
0
Timer10X:
Enables the software to easily scale the TimerClock
period by a factor of 10 to match a 10 Mbits/sec or 100 Mbits/sec
environment. When this bit is set, T
X
C
LK
is divided by 20 to create
T
IMER
C
LOCK
, otherwise it is divided by 2. The division by 20 is used
when the AIC-6915 operates at line speed of 100 Mbits/Sec.
10:9
r/w
0
SmallRxFrame:
Defines the size of a received Ethernet frame that is
considered ‘small’. The AIC-6915 interrupts ‘small’ frames earlier
than normal frames if SmallFrameBypass bit is set.
‘00’ - ‘Small’ frame when less or equal to 64 bytes
‘01’ - ‘Small’ frame when less or equal to 128 bytes
‘10’ -‘Small’ frame when less or equal to 256 bytes
‘11’ - ‘Small’ frame when less or equal to 512 bytes
8
r/w
0
SmallFrameBypass:
When this bit is set, AND the receive interrupt
masking timer is active, and the interrupt status bit R
X
D
ONE
I
NT
is
set as a result of receiving and completing the DMA transfer of a
‘small’ frame, then R
X
D
ONE
I
NT
by-passes the masking timer and
asserts the external PCI interrupt line. When S
MALL
F
RAME
B
YPASS
is
reset, the AIC-6915 treats all received frames the same. It does not
assert the external interrupt line if the interrupt masking timer is
active.
7
r
0
Reserved: Always read as ‘0’.
6:5
r/w
0
IntMaskMode:
Controls the operation of the interrupt masking
timer.
‘00’ - The timer is not loaded.
‘01’ - When this value is written, the timer is loaded with the
number defined by IntMaskPeriod. The timer is decremented
by one every rising edge of T
IMER
C
LOCK
. During a masking-
period, active (asserted) Transmit and Receive Interrupts are
masked and do not cause an assertion of an interrupt on the
PCI bus. When the timer reaches its terminal count (0) the
interrupts are enabled.
‘10’ - Same as ‘01’, except that new masking period starts
automatically when the software driver clears both
T
X
D
ONE
I
NT
and R
X
D
ONE
I
NT
.
‘11’ - Same as ‘01’, except that new masking period starts
automatically when first asserting a new interrupt. In this case
the masking period is extended by the time interval from the
last time the software cleared the interrupt until a new one is
asserted.
Table 7-40. TimersControl Register (Continued)
Bit(s)
rw
Reset
value
Description/Function
