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AIC-6915 Ethernet LAN Controller Programmer’s Manual
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There are three kinds of interrupts generated by the transmit DMA engine. A
“TxDmaDoneInt” is generated when the entire packet is DMA-transferred. A
“TxFrameCompleteInterrupt” is generated when an entire packet is transmitted.
There are two control bits, DisableTxDmaCompletion and
DmaCompletionAfterTransmitComplete defined in the TxDescQueueCtrl and
TxFrameControl registers to enable and disable each one of them. Setting these
interrupt status bits is also conditioned with the
INTR
control bit in the transmit
descriptor. A third interrupt, “TxQueueDoneInterrupt”, is generated only when the
descriptor queue is empty.
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Completion queue address control is centralized in the Completion Module for both
receive and transmit. There are separate Completion Queues for receive and
transmit. However, extra logic is built in the Completion Module to handle one
Completion Queue for both receive and transmit. The Completion Queue size is
1024 entries. Each entry is either one word or two words, defined by driver at
initialization time. The Completion Queue is aligned at 256-byte boundary. There is a
Completion Queue Threshold defined in the register. When the free entries in the
Completion Queue fall below this threshold, an interrupt is generated. The software
driver should update the consumer index of the completion queue when it detects
that the interrupt status bit is set.
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A Transmit DMA operation is triggered when there are frames in the descriptor
queues and when the FIFO has room for “DMA Burst Size”, a register defined by the
software driver during initialization. The transmit DMA module dynamically
adjusts DMA burst size so that DMA operations end on cache line boundaries. This
can improve bus utilization on DMA data transfers.
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The “Frame Processor (FP) FIFO Engine” in the transmit DMA block works with FP
to calculate TCP/UDP checksum for transmit packets. The checksum calculation
starts when the DMA engine fetches the first burst of transmit data from Bus Access
Control (BAC) and works in parallel during the DMA-transfer of the packet. Actual
transmission to the MAC is not enabled until the checksum calculation is finished.
For non-TCP/UDP packets, the driver can set the
CALTCP
bit to zero in the
descriptor to disable checksum calculation and the transmission to the MAC can
start without waiting for the end of packet. After the Transmit DMA fetches the first
burst of transmit data, it signals the FP FIFO engine to begin reading packet data
from the FIFO bus and passes that data to FP 16-bits at a time. The FP FIFO Engine
decodes the write pointer of the FIFO to make sure that it does not read past the
valid data of transfer. At the end of the packet, the DMA-transfer terminates and the
FP FIFO Engine waits for the checksum and address of checksum returned by the FP.
The FP FIFO engine writes the checksum to the FIFO, signals the transmit frame to
start transmitting the packet, and signals the transmit DMA engine to start reading
the next packet.
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Internal 4 KByte dedicated transmit FIFO. The FIFO is implemented by a dual-port
SRAM. Once the port is written by the BAC, the other port is shared by the transmit
and receive blocks.
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Packets in the internal FIFO are handled by link-lists. Transmit DMA block can DMA
as many packets as possible into the FIFO as long as there is enough space.
