372
Pulse counter logic (PC)
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The BLOCK and TMIT_VAL inputs can be connected to Single Command blocks,
which are intended to be controlled either from the station HMI or/and the local HMI.
As long as the BLOCK signal is set, the pulse counter is blocked. The signal connected
to TMIT_VAL performs one additional reading per positive flank. The signal must be
a pulse with a length >1 second.
The BIM_CONN input is connected to the used input of the function block for the Bi-
nary Input Module (BIM). If BIM_CONN is connected to another function block, the
INVALID signal is activated to indicate the configuration error.
The NAME input is used for a user-defined name with up to 19 characters.
Each pulse counter function block has four output signals: INVALID, RESTART,
BLOCKED, and NEW_VAL. These signals can be connected to an Event function
block for event recording.
The INVALID signal is a steady signal and is set if the Binary Input Module, where the
pulse counter input is located, fails or has wrong configuration.
The RESTART signal is a steady signal and is set when the reported value does not
comprise a complete integration cycle. That is, in the first message after terminal start-
up, in the first message after deblocking, and after the counter has wrapped around dur-
ing last integration cycle.
The BLOCKED signal is a steady signal and is set when the counter is blocked. There
are two reasons why the counter is blocked:
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The BLOCK input is set, or
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The Binary Input Module, where the counter input is situated, is inoperative.
The NEW_VAL signal is a pulse signal. The signal is set if the counter value was up-
dated since last report.
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From the PST Parameter Setting Tool under SETTINGS/PC01-12 (Pulse Counter) in
the terminal tree, these parameters can be set individually for each pulse counter:
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Operation = Off/On
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Cycle Time = 30s / 1min / 1min30s / 2min / 2min30s / 3min / 4min / 5min / 6min /
7min30s / 10min / 12min / 15min / 20min / 30min / 60min.
Summary of Contents for REO 517
Page 10: ... RQWHQWV ...
Page 16: ...6 Introduction to the application manual KDSWHU QWURGXFWLRQ ...
Page 64: ...54 Blocking of signals during test KDSWHU RPPRQ IXQFWLRQV ...
Page 88: ...78 Scheme communication logic ZCOM KDSWHU LQH LPSHGDQFH ...
Page 146: ...136 Unbalance protection for capacitor banks TOCC KDSWHU XUUHQW ...
Page 166: ...156 Dead line detection DLD KDSWHU 3RZHU V VWHP VXSHUYLVLRQ ...
Page 378: ...368 Monitoring of DC analog measurements KDSWHU 0RQLWRULQJ ...
Page 384: ...374 Pulse counter logic PC KDSWHU 0HWHULQJ ...
Page 412: ...402 Serial communication modules SCM KDSWHU DWD FRPPXQLFDWLRQ ...
Page 440: ...430 LED indication module KDSWHU DUGZDUH PRGXOHV ...