281
Interlocking
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For a breaker-and-a-half arrangement, the modules BH_LINE_A, BH_CONN and
BH_LINE_B must be used.
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For application without Q9 and Q8, just set the appropriate inputs to open state and dis-
regard the outputs. In the functional block diagram, 0 and 1 are designated 0=FIXD-
OFF and 1=FIXD-ON:
•
Q9_OP = 1
•
Q9_CL = 0
•
Q8_OP = 1
•
Q8_CL = 0
If, in this case, a line voltage supervision is added, then rather than setting Q9 to open
state, specify the state of the voltage supervision:
•
Q9_OP = VOLT_OP
99000360.vsd
Q1
Q51
Q52
Q0
Q6
Q9
Q8
Q2
Q51
Q52
Q0
Q6
Q53
Q53
Q61
Q62
Q0
Q9
Q8
Q51
Q52
BH_CONN
BH_LINE_B
BH_LINE_A
A (BB1)
B (BB2)
Summary of Contents for REO 517
Page 10: ... RQWHQWV ...
Page 16: ...6 Introduction to the application manual KDSWHU QWURGXFWLRQ ...
Page 64: ...54 Blocking of signals during test KDSWHU RPPRQ IXQFWLRQV ...
Page 88: ...78 Scheme communication logic ZCOM KDSWHU LQH LPSHGDQFH ...
Page 146: ...136 Unbalance protection for capacitor banks TOCC KDSWHU XUUHQW ...
Page 166: ...156 Dead line detection DLD KDSWHU 3RZHU V VWHP VXSHUYLVLRQ ...
Page 378: ...368 Monitoring of DC analog measurements KDSWHU 0RQLWRULQJ ...
Page 384: ...374 Pulse counter logic PC KDSWHU 0HWHULQJ ...
Page 412: ...402 Serial communication modules SCM KDSWHU DWD FRPPXQLFDWLRQ ...
Page 440: ...430 LED indication module KDSWHU DUGZDUH PRGXOHV ...