Reference Voltage
The 1.8V rail connected to the DVdd pincan also be connected to the AVdd pin. This connection will make
the device function, but the achievable performance is a function of the voltage ripple typically found on
DC-DC converter outputs. To achieve specified performance, an external low-input-voltage 1.6V LDO
must be connected between the 1.8V rail and the AVdd input.
During operation, the AVdd LDO is deactivated via control register Page 1 / Register 2, D(0)=0. In this
case the LDOin pin should be connected to DVdd.
2.9.1.1.1 Standby Mode (1.8V operation)
To put the device in standby mode, both external voltages (AVdd and DVdd) and the reference block
inside the TLV320DAC3203 must stay on (Page 1 / Register 123, D(2:0) = 101), all other blocks should be
powered down. This results in standby current of approximately 100
μ
A from the AVdd supply.
In standby mode the device responds very quickly to playback requests.
2.9.1.1.2 Sleep Mode (1.8V operation)
In this mode, all settings and memory content of the device is retained. To put the device into sleep mode,
the external DVdd must remain powered up, the external AVdd LDO must be powered down, the crude
AVdd generation must be turned on (Pg 1, Reg 1, D(3)=0) and the analog blocks must be powered down
(Pg 1, Reg 2, D(3)=1). The device's sleep mode power consumption in this case is < 1.5
μ
A
2.9.1.1.3 Shutdown Mode
To shut down the device, the external supplies can be turned off completely. If the 1.8V rail cannot be
turned off, the crude AVdd generation must be turned on (Pg 1, Reg 1, D(3)=0) and the analog blocks
must be powered down (Pg 1, Reg 2, D(3)=1). This results in a device shutdown current < 1.5
μ
A.
2.9.1.2
Other Supply Options
There are other options to power the device. Apply the following rules:
•
During normal operation all supply pins must be connected to a supply (via internal LDO or external)
•
Whenever the LDOin supply is present,
–
DVdd supply must be present as well
–
If AVdd supply is not present, then the crude internal AVdd generation must be turned on (Pg 1,
Reg 1, D(3)=0)
•
Whenever the DVdd supply is on, and either AVdd or LDOin or both supplies are off, the analog blocks
must be powered down (Pg 1, Reg 2, D(3)=1)
2.10 Reference Voltage
All data converters require a DC reference voltage. The TLV320DAC3203 achieves its low-noise
performance by internally generating a low-noise reference voltage. This reference voltage is generated
using a band-gap circuit with a good PSRR performance. This reference voltage must be filtered
externally using a minimum 1
μ
F capacitor connected from the REF pin to analog ground (AVss).
This reference block is powered down when all analog blocks inside the device are powered down. In this
condition, the REF pin is 3-stated. On powerup of any analog block, the reference block is also powered
up and the REF pin settles to its steady-state voltage after the settling time (a function of the de-coupling
capacitor on the REF pin). This time is approximately equal to 1 second when using a 1
μ
F decoupling
capacitor. In the event that a faster power-up is required, either the reference block can be kept powered
up (even when no other analog block is powered up) by programming Page 1, Register 123, D(2) = 1.
However, in this case, an additional 125
μ
A of current from AVdd is consumed. Additionally, to achieve a
faster powerup, a fast-charge option is also provided where the charging time can be controlled between
40ms and 120ms by programming Page 1, Register 123, D(1:0). By default, the fast charge option is
disabled.
70
TLV320DAC3203 Application
SLAU434 – May 2012
Copyright © 2012, Texas Instruments Incorporated
