DAC
PRB_Rx, AOSR, NADC, MADC, common mode setting
Additionally if the PLL is used the PLL parameters P, J, D and R are determined as well.
Step 2
Setting up the device via register programming:
The following list gives a sequence of items that must be executed between powering the device up and
reading data from the device:
Define starting point:
Set register page to 0
Initiate SW Reset
Program Clock Settings Program PLL clock dividers P,J,D,R (if PLL is necessary)
Power up PLL (if PLL is necessary)
Program and power up NADC
Program and power up MADC
Program OSR value
Program the processing block to be used
At this point, at the latest, analog power supply must be applied to the device (via internal LDO or
external)
Program Analog Blocks Set register Page to 1
Disable coarse AVdd generation
Enable Master Analog Power Control
A detailed example can be found in
2.4
DAC
The TLV320DAC3203 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each
channel of the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a
digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The
DAC is designed to provide enhanced performance at low sampling rates through increased oversampling
and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and
signal images strongly suppressed within the audio band to beyond 20kHz. To handle multiple input rates
and optimize performance, the TLV320DAC3203 allows the system designer to program the oversampling
rates over a wide range from 1 to 1024. The system designer can choose higher oversampling ratios for
lower input data rates and lower oversampling ratios for higher input data rates.
The TLV320DAC3203 DAC channel includes a built-in digital interpolation filter to generate oversampled
data for the sigma-delta modulator. The interpolation filter can be chosen from three different types
depending on required frequency response, group delay and sampling rate.
The DAC path of the TLV320DAC3203 features many options for signal conditioning and signal routing:
•
Digital volume control with a range of -63.5 to +24dB
•
Mute function
•
Dynamic range compression (DRC)
In addition to the standard set of DAC features the TLV320DAC3203 also offers the following special
features:
•
Built in sine wave generation (beep generator)
•
Digital auto mute
•
Adaptive filter mode
The TLV320DAC3203 implements signal processing capabilities and interpolation filtering via processing
blocks. These fixed processing blocks give users the choice of how much and what type of signal
processing they may use and which interpolation filter is applied.
gives an overview over all available processing blocks of the DAC channel and their
properties.
35
SLAU434 – May 2012
TLV320DAC3203 Application
Copyright © 2012, Texas Instruments Incorporated
