Control Interfaces
The D-divider value is 14-bits wide and is controlled by 2 registers. For proper update of the D-divider
value, Page 0, Register 7 must be programmed first followed immediately by Page 0, Register 8. Unless
the write to Page 0, Register 8 is completed, the new value of D will not take effect.
The clocks for codec and various signal processing blocks, CODEC_CLKIN can be generated from MCLK
input, BCLK input, GPIO input or PLL_CLK (Page 0/Register 4/D(1:0) ).
If the CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down
last.
lists several example cases of typical MCLK rates and how to program the PLL to achieve a
sample rate Fs of either 44.1kHz or 48kHz.
Table 2-23. PLL Example Configurations
Fs = 44.1kHz
MCLK (MHz)
PLLP
PLLR
PLLJ
PLLD
MADC
NADC
AOSR
MDAC
NDAC
DOSR
2.8224
1
3
10
0
3
5
128
3
5
128
5.6448
1
3
5
0
3
5
128
3
5
128
12
1
1
7
560
3
5
128
3
5
128
13
1
2
4
2336
13
3
64
4
6
104
16
1
1
5
2920
3
5
128
3
5
128
19.2
1
1
4
4100
3
5
128
3
5
128
48
4
1
7
560
3
5
128
3
5
128
Fs = 48kHz
2.048
1
3
14
0
2
7
128
7
2
128
3.072
1
4
7
0
2
7
128
7
2
128
4.096
1
3
7
0
2
7
128
7
2
128
6.144
1
2
7
0
2
7
128
7
2
128
8.192
1
4
3
0
2
8
128
4
4
128
12
1
1
7
1680
2
7
128
7
2
128
16
1
1
5
3760
2
7
128
7
2
128
19.2
1
1
4
4800
2
7
128
7
2
128
48
4
1
7
1680
2
7
128
7
2
128
2.8
Control Interfaces
The TLV320DAC3203 control interface supports SPI or I
2
C communication protocols, with the protocol
selectable using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I
2
C, SPI_SELECT
should be tied low. It is not recommended to change the state of SPI_SELECT during device operation.
2.8.1 I
2
C Control Mode
The TLV320DAC3203 supports the I
2
C control protocol, and will respond to the I
2
C address of 0011000.
I
2
C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices
on the I
2
C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines
HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no
device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus
simultaneously, there is no driver contention.
Communication on the I
2
C bus always takes place between two devices, one acting as the master and the
other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under
the direction of the master. Some I
2
C devices can act as masters or slaves, but the TLV320DAC3203 can
only act as a slave device.
An I
2
C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock.
All data is transmitted across the I
2
C bus in groups of eight bits. To send a bit on the I
2
C bus, the SDA line
is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero, while a HIGH
indicates the bit is one).
66
TLV320DAC3203 Application
SLAU434 – May 2012
Copyright © 2012, Texas Instruments Incorporated
