LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
3
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N N
N N N
N N N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N N
N N N
N N N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Audio Digital I/O Interface
2.6.2 Left Justified Mode
The Audio Interface of the TLV320DAC3203 can be put into Left Justified Mode by programming Page 0,
Register 27, D(7:6) = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge of
the bit clock following the falling edge of the word clock. Similarly the MSB of the left channel is valid on
the rising edge of the bit clock following the rising edge of the word clock.
Figure 2-35. Timing Diagram for Left-Justified Mode
Figure 2-36. Timing Diagram for Left-Justified Mode with Offset=1
Figure 2-37. Timing Diagram for Left-Justified Mode with Offset=0 and inverted bit clock
For Left-Justified mode, the number of bit-clocks per frame should be greater than twice the programmed
word-length of the data. Also, the programmed offset value should be less than the number of bit-clocks
per frame by at least the programmed word-length of the data.
58
TLV320DAC3203 Application
SLAU434 – May 2012
Copyright © 2012, Texas Instruments Incorporated
