DAC
DAC running
Page 44 / Reg 1, Bits D1
Coefficient Buffer in use
Writing to
Will update
No
0
None
C1, Buffer A
C1, Buffer A
No
0
None
C1, Buffer B
C1, Buffer B
Yes
0
Buffer A
C1, Buffer A
C1, Buffer B
Yes
0
Buffer A
C1, Buffer B
C1, Buffer B
Yes
1
Buffer B
C1, Buffer A
C1, Buffer A
Yes
1
Buffer B
C1, Buffer B
C1, Buffer A
The user programmable coefficients C1 to C70 are defined on Pages 44, 45 and 46 for Buffer A and
Pages 62, 63 and 64 for Buffer B.
2.4.6 DAC Setup
The following paragraphs are intended to guide a user through the steps necessary to configure the
TLV320DAC3203 DAC.
Step 1
The system clock source (master clock) and the targeted DAC sampling frequency must be identified.
Depending on the targeted performance the decimation filter type (A, B or C) and DOSR value can be
determined.
Filter A should be used for 48kHz high-performance operation, DOSR must be a multiple of 8.
Filter B should be used for up to 96kHz operations, DOSR must be a multiple of 4.
Filter C should be used for up to 192kHz operations, DOSR must be a multiple of 2.
In all cases the DOSR is limited in its range by the following condition:
2.8MHz < DOSR * DAC_FS < 6.2MHz
Based on the identified filter type and the required signal processing capabilities, the appropriate
processing block can be determined from the list of available processing blocks (PRB_P1 to PRB_P25).
Based on the available master clock, the chosen DOSR and the targeted sampling rate, the clock divider
values NDAC and MDAC can be determined. If necessary, the internal PLL can add a large degree of
flexibility.
In summary, Codec_Clkin (derived directly from the system clock source or from the internal PLL) divided
by MDAC, NDAC and DOSR must be equal to the DAC sampling rate DAC_FS. The codec_clkin clock
signal is shared with the ADC clock generation block.
CODEC_CLKIN = NDAC*MDAC*DOSR*DAC_FS
To a large degree, NDAC and MDAC can be chosen independently in the range of 1 to 128. In general,
NDAC should be as large as possible as long as the following condition can still be met:
MDAC*DOSR/32
≥
RC
RC is a function of the chosen processing block and is listed in
The common-mode voltage setting of the device is determined by the available analog power supply. This
common-mode (input common-mode) value is common across the ADC, DAC and analog bypass path.
The output common-mode setting is determined by the available analog power supplies (AVdd and ) and
the desired output-signal swing.
At this point the following device specific parameters are known:
PRB_Px, DOSR, NDAC, MDAC, input and output common-mode values
If the PLL is used, the PLL parameters P, J, D and R are determined as well.
48
TLV320DAC3203 Application
SLAU434 – May 2012
Copyright © 2012, Texas Instruments Incorporated
