Audio Digital I/O Interface
2.5.2.10 DAC, Stereo, 192kHz, Lowest Power Consumption
DOSR = 16, Processing Block = PRB_P17 (Interpolation Filter C), PowerTune Mode = PTM_P1, DVdd =
1.26V
CM = 0.75V
CM = 0.9V
UNIT
AVdd=1.5V
AVdd=1.8V
0dB full scale
(1)
75
100
mV
RMS
HP out
Effective SNR w.r.t.
88.3
90.6
dB
(32
Ω
load)
0dB full scale
Power consumption
6.0
6.7
mW
(1)
Reduced 0dB full-scale swing can be compensated by applying appropriate gain in the output drivers see .
Alternative processing blocks:
Processing Block
Filter
Est. Power Change (mW)
PRB_P18
C
+4.5
PRB_P19
C
+1.5
2.6
Audio Digital I/O Interface
Audio data is transferred between the host processor and the TLV320DAC3203 via the digital audio data
serial interface, or audio bus. The audio bus on this device is very flexible, including left or right-justified
data options, support for I
2
S or PCM protocols, programmable data length options, a TDM mode for
multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to
communicate with multiple devices within a system directly.
The audio bus of the TLV320DAC3203 can be configured for left or right-justified, I
2
S, DSP, or TDM
modes of operation, where communication with standard PCM interfaces is supported within the TDM
mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
configuring Page 0, Register 27, D(5:4). In addition, the word clock and bit clock can be independently
configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The
word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a
square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and
DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in Page 0, Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate
various word-lengths as well as to support the case when multiple TLV320DAC3203s may share the same
audio bus.
The TLV320DAC3203 also includes a feature to offset the position of start of data transfer with respect to
the word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in
Page 0, Register 28.
The TLV320DAC3203 also has the feature of inverting the polarity of the bit-clock used for transferring the
audio data as compared to the default clock polarity used. This feature can be used independently of the
mode of audio interface chosen. This can be configured via Page 0, Register 29, D(3).
The TLV320DAC3203 further includes programmability (Page 0, Register 27, D0) to place the DOUT line
into a hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this
capability with the ability to program at what bit clock in a frame the audio data begins, time-division
multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data
bus. When the audio serial data bus is powered down while configured in master mode, the pins
associated with the interface are put into a hi-Z output condition.
56
TLV320DAC3203 Application
SLAU434 – May 2012
Copyright © 2012, Texas Instruments Incorporated
