LD(n)
LD (n+1)
BIT
CLOCK
DATA
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
0
3
2
1
N
-
1
N
-
2
N
-
3
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
LD(n)
LD(n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
0
3
2
1
-
1
-
2
N N N
N N N
N N N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
LD(n)
LD (n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
0
3
2
1
-
1
-
2
N N N
N N N
N N N
-
3
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Audio Digital I/O Interface
2.6.4 DSP Mode
The Audio Interface of the TLV320DAC3203 can be put into DSP Mode by programming Page 0, Register
27, D(7:6) = 01. In DSP mode, the rising edge of the word clock starts the data transfer with the left
channel data first and immediately followed by the right channel data. Each data bit is valid on the falling
edge of the bit clock.
Figure 2-41. Timing Diagram for DSP Mode
Figure 2-42. Timing Diagram for DSP Mode with offset = 1
Figure 2-43. Timing Diagram for DSP Mode with offset = 0 and bit clock inverted
For DSP mode, the number of bit-clocks per frame should be greater than twice the programmed word-
length of the data. Also the programmed offset value should be less than the number of bit-clocks per
frame by at least the programmed word-length of the data.
60
TLV320DAC3203 Application
SLAU434 – May 2012
Copyright © 2012, Texas Instruments Incorporated
