Digital Microphone Input/Decimation Filter
2.3.3.2.3 Adaptive Filtering
After the ADC is running, the filter coefficients are locked and cannot be accessed for read or write.
However the TLV320DAC3203 offers an adaptive filter mode as well. Setting Register Page 8,Reg 1,
D(2)=1 turns on double buffering of the coefficients. In this mode filter coefficients can be updated through
the host and activated without stopping and restarting the ADC, enabling advanced adaptive filtering
applications.
To support double buffering, all coefficients are stored in two buffers (Buffer A and B). When the ADC is
running and adaptive filtering mode is turned on, setting the control bit Page 8, Reg 1,D(0)=1 switches the
coefficient buffers at the next start of a sampling period. The bit reverts to 0 after the switch occurs. At the
same time, the flag Page 8, Reg 1, D(1) toggles.
The flag in Page 8, Reg 1, D(1) indicates which of the two buffers is actually in use.
Page 8, Reg 1, D(1)=0: Buffer A is in use by the ADC engine, D(1)=1: Buffer B is in use.
While the device is running, coefficient updates are always made to the buffer not in use by the ADC,
regardless to which buffer the coefficients have been written
ADC running
Flag, Page 8, Reg 1, D(1)
Coefficient Buffer in use
Writing to
Will update
No
0
None
C4, Buffer A
C4, Buffer A
No
0
None
C4, Buffer B
C4, Buffer B
Yes
0
Buffer A
C4, Buffer A
C4, Buffer B
Yes
0
Buffer A
C4, Buffer B
C4, Buffer B
Yes
1
Buffer B
C4, Buffer A
C4, Buffer A
Yes
1
Buffer B
C4, Buffer B
C4, Buffer A
2.3.3.3
Setup
The following discussion is intended to guide a system designer through the steps necessary to configure
the TLV320DAC3203 ADC.
Step 1
The system clock source (master clock) and the targeted ADC sampling frequency must be identified.
The oversampling ratio (OSR) of the TLV320DAC3203 must be configured to match the properties of the
digital microphone.
Based on the identified filter type and the required signal processing capabilities the appropriate
processing block can be determined from the list of available processing blocks (PRB_R1 to PRB_R18)
(See
Based on the available master clock, the chosen OSR and the targeted sampling rate, the clock divider
values NADC and MADC can be determined. If necessary the internal PLL will add a large degree of
flexibility.
In summary, Codec_Clkin which is either derived directly from the system clock source or from the internal
PLL, divided by MADC, NADC and AOSR, must be equal to the ADC sampling rate ADC_FS. The
codec_clkin clock signal is shared with the DAC clock generation block.
CODEC_CLKIN = NADC*MADC*AOSR*ADC_FS
To a large degree NADC and MADC can be chosen independently in the range of 1 to 128. In general
NADC should be as large as possible as long as the following condition can still be met:
MADC*AOSR/32
≥
RC
RC is a function of the chosen processing block, and is listed in
The common mode setting of the device is determined by the available analog power supply and the
desired PowerTune mode, this common mode setting is shared across DAC (input common mode) and
analog bypass path.
At this point the following device specific parameters are known:
34
TLV320DAC3203 Application
SLAU434 – May 2012
Copyright © 2012, Texas Instruments Incorporated
