DAC
Table 2-19. DRC HPF and LPF Coefficients (continued)
Coefficient
Location
LPF D1
C76 Page 46, Register 72 to 75
The default values of these coefficients implement a high-pass filter with a cut-off at 0.00166*DAC_FS,
and a low-pass filter with a cutoff at 0.00033*DAC_FS.
The output of the DRC high-pass filter is fed to the Processing Block selected for the DAC Channel. The
absolute value of the DRC-LPF filter is used for energy estimation within the DRC.
The gain in the DAC Digital Volume Control is controlled by Page 0, Register 65 and 66. When the DRC is
enabled, the applied gain is a function of the Digital Volume Control register setting and the output of the
DRC.
The DRC parameters are described in sections that follow.
2.4.4.2.1 DRC Threshold
The DRC Threshold represents the level of the DAC playback signal at which the gain compression
becomes active. The output of the digital volume control in the DAC is compared with the set threshold.
The threshold value is programmable by writing to register Page 0, Register 68, Bits D4-D2). The
Threshold value can be adjusted between –3dBFS to -24dBFS in steps of 3dB. Keeping the DRC
Threshold value too high may not leave enough time for the DRC block to detect peaking signals, and can
cause excessive distortion at the outputs. Keeping the DRC Threshold value too low can limit the
perceived loudness of the output signal.
The recommended DRC-Threshold value is –24 dB.
When the output signal exceeds the set DRC Threshold, the interrupt flag bits at Page 0, Register 44, Bits
D3-D2) are updated. These flag bits are 'sticky' in nature, and are reset only after they are read back by
the user. The non-sticky versions of the interrupt flags are also available at Page 0, Register 46, Bits D3-
D2).
2.4.4.2.2 DRC Hysteresis
DRC Hysteresis is programmable by writing to Page 0, Register 68, Bits D1-D0). It can be programmed to
values between 0dB and 3dB in steps of 1dB. It is a programmable window around the programmed DRC
Threshold that must be exceeded for a disabled DRC to become enabled, or an enabled DRC to become
disabled. For example, if the DRC Threshold is set to -12dBFS and DRC Hysteresis is set to 3dB, then if
the gain compressions in the DRC is inactive, the output of the DAC Digital Volume Control must exceed
–9dBFS before gain compression due to the DRC is activated. Similarly, when the gain compression in
the DRC is active, the output of the DAC Digital Volume Control needs to fall below -15dBFS for gain
compression in the DRC to be deactivated. The DRC Hysteresis feature prevents the rapid activation and
de-activation of gain compression in the DRC in cases when the output of DAC Digital Volume Control
rapidly fluctuates in a narrow region around the programmed DRC Threshold. By programming the DRC
Hysteresis as 0dB, the hysteresis action is disabled.
Recommended Value of DRC Hysteresis is 3 dB.
2.4.4.2.3 DRC Hold
The DRC Hold is intended to slow the start of decay for a specified period of time in response to a
decrease in energy level. To minimize audible artifacts, it is recommended to set the DRC Hold time to 0
through programming Page 0, Register 69, Bits D6-D3) = 0000.
45
SLAU434 – May 2012
TLV320DAC3203 Application
Copyright © 2012, Texas Instruments Incorporated
