4.18
SEL-387-0, -5, -6 Relay
Instruction Manual
Date Code 20170601
Control Logic
Trip and Close Logic
The other unlatching mechanism is manual, via pushing of the
{TARGET RESET}
pushbutton on the front panel or sending the
TAR R
serial port command to
the relay. Either of these asserts the Relay Word bit TRGTR, which is also
used to reset the LED targets on the front panel. In the trip logic, assertion of
ULTR1 or TRGTR places a zero input on the AND gate and thereby breaks
the TRIP1 seal-in loop.
With the deassertion of TRIP1,
OUT101
opens, de-energizing the trip circuit.
Presumably, the trip circuit current has already been interrupted by a breaker
52a contact in series with the trip coil. Should a failure to trip occur, followed
by backup tripping of other breakers, the TR1 setting may deassert and the
ULTR1 setting may assert, while the contact continues to carry dc trip circuit
current. This could damage the contact as it tries to interrupt this current. The
emergency nature of the situation might warrant this minor risk, but another
choice might be to program into the ULTR1 setting not only removal of
current but also indication that the breaker has opened.
Note that TRIP1 will always be asserted so long as TR1 is asserted, regardless
of the action of ULTR1 or the
TARGET RESET
commands and that TRIP1
will be asserted for an absolute minimum of TDURD cycles no matter how
short the length of time TR1 has been asserted. This is the essence of the trip
logic.
is an additional OR gate. The five TRIP
m
Relay
Word bits are all inputs to this gate, and the output is another Relay Word bit,
TRIPL. TRIPL asserts for any trip output. It may be useful for other
applications of SEL
OGIC
control equations in the SEL-387.
Close Logic
There are four specific sets of close logic within the SEL-387. They are
designed to operate when SEL
OGIC
control equation close variable setting
CL
m
is asserted (
m
= 1, 2, 3, 4), and to unlatch when SEL
OGIC
control
equation setting ULCL
m
is asserted. The output of the logic is Relay Word bit
CLS
m
. The logic operates much like the Latch Bit function in SEL
OGIC
Control Equation Sets 1 through 3 with additional characteristics. In the close
logic, the reset or unlatch function has priority over the set or latch function.
shows the logic diagram for the CLS1 logic. The remaining logic
for CLS2 through CLS4 is identical, using variables CL2 through CL4 and
ULCL2 through ULCL4, respectively.
Figure 4.8
SEL-387 Close Logic (CLS1)
The logic begins with the assertion of SEL
OGIC
control equation CL1, one of
the Group variables. In our example application, CL1 = CC1 + /IN104. Thus,
CL1 will assert either if (1) a
CLO 1
command has been sent to the relay via a
Relay
Word
Bits
CLS1
Close
Failure Timer
CF1T
0
CFD
Logical 1 (setting CFD
≠
OFF;
Close Failure Timer Operative)
Close Failure Timer Inoperative)
Logical 0 (setting CFD = OFF;
CL1
ULCL1
52A1
Pulses
(logical 1) for
one processing
interval if
Close Failure
Timer times out
rising
edge detect
SEL
OGIC
Control
Equation Settings
Содержание SEL-387-0
Страница 6: ...This page intentionally left blank ...
Страница 12: ...This page intentionally left blank ...
Страница 50: ...This page intentionally left blank ...
Страница 200: ...This page intentionally left blank ...
Страница 248: ...This page intentionally left blank ...
Страница 380: ...This page intentionally left blank ...
Страница 422: ...This page intentionally left blank ...
Страница 440: ...This page intentionally left blank ...
Страница 458: ...This page intentionally left blank ...
Страница 516: ...This page intentionally left blank ...
Страница 540: ...This page intentionally left blank ...