Renesas RX100 Series, Руководство пользователя

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R01UH0822EJ0100 Rev.1.00 Page 1006 of 1041
Jul 31, 2019
RX13T Group 32. Electrical Characteristics
32.4.5 Timing of On-Chip Peripheral Modules
Note 1. t
Pcyc
: PCLK cycle
Note 2. t
cac
: CAC count clock source cycle
Table 32.28 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VCC to 5.5 V, VSS = AVSS0 = 0 V, T
a
= –40 to +105°C
Item Symbol Min. Max. Unit
*1
Test Conditions
I/O ports Input data pulse width t
PRW
1.5 — t
Pcyc
Figure 32.18
MTU Input capture input pulse width Single-edge setting t
TICW
1.5 — t
Pcyc
Figure 32.19
Both-edge setting 2.5 —
Timer clock pulse width Single-edge setting t
TCKWH
,
t
TCKWL
1.5 — Figure 32.20
Both-edge setting 2.5 —
Phase counting mode 2.5 —
POE POE# input pulse width t
POEW
1.5 — t
Pcyc
Figure 32.21
Output disable time Transition of the POE# signal level t
POEDI
— 5 t
Pcyc
+ 0.24 μs Figure 32.22
In the case of falling-
edge detection
(ICSRm.POEnM[3:0]
= 0000 (m =1, 3, 4;
n = 0, 8,10))
Simultaneous conduction of output pins t
POEDO
— 3 t
Pcyc
+ 0.2 Figure 32.23
Detection of comparator outputs t
POEDC
— 5 t
Pcyc
+ 0.2 Figure 32.24
When the noise filter
for a comparator C is
not in use
(CMPCTL.CDFS[1:0]
= 00), and the values
exclude the time until
the level of the
detection signal
changes after a
comparator C detects
the required change
in voltage.
Register setting t
POEDS
— 1 t
Pcyc
+ 0.2 Figure 32.25
Time for access to the
register is not
included.
Oscillation stop detection t
POEDOS
— 21 Figure 32.26
SCI Input clock cycle Asynchronous t
Scyc
4 — t
Pcyc
Figure 32.27
Clock synchronous 6 —
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 20 ns
Input clock fall time t
SCKf
— 20
Output clock cycle Asynchronous t
Scyc
16 — t
Pcyc
Figure 32.28
C = 30 pF
Clock synchronous 4 —
Output clock pulse width t
SCKW
0.4 0.6 t
Scyc
Output clock rise time t
SCKr
— 20 ns
Output clock fall time t
SCKf
— 20
Transmit data delay time
(master) Clock synchronous t
TXD
— 40
Transmit data delay time
(slave) Clock
synchronous VCC = 4.0 V or above — 40
VCC = 2.7 V or above — 65
Receive data setup time
(master) Clock
synchronous VCC = 4.0 V or above t
RXS
40 —
VCC = 2.7 V or above 65 —
Receive data setup time
(slave) Clock synchronous 40 —
Receive data hold time Clock synchronous t
RXH
40 —
A/D converter Trigger input pulse width t
TRGW
1.5 — t
Pcyc
Figure 32.29
CAC CACREF input pulse width t
Pcyc
≤ t
cac
*2
t
CACREF
4.5 t
cac
+ 3 t
Pcyc
— ns
t
Pcyc
> t
cac
*2
5 t
cac
+ 6.5 t
Pcyc