NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
206 of 345
For more details about the pins and power supply, refer to the PN7462 family datasheet.
For deeper description of usage of each pin, please refer to the PN7462 family contact
interface application note.
13.4 Specific blocks
13.4.1 ATR counter
The sequencer manages the activation and deactivation sequences. In addition to the
sequencer, the ATR counter is used to manage RST and check the asynchronous card
ATR on the full slot. In case of synchronous cards, RST is controlled via RSTIN bit (see
the registers description) and the card ATR is not checked. The operating mode
(asynchronous or synchronous) has to be selected by the application (see the registers
description).
The ATR counter block is composed of two counters. One checks the early answer and
the second checks if the card is mute.
The early answer counter is composed of a fixed part that counts up to 200d CLK cycles.
An additional part counts up to EC7-EC0 bits value CLK cycles (see the registers
description). The default value of EC7-EC0 bits is 170d, which gives a total default count
of 370d CLK cycles. The additional configurable count enables to follow a potential
standard change.
The mute counter counts up to MCL15-MCL0 bits value CLK cycles when RST is LOW
and up to MCH15-MCH0 bits value CLK cycles when RST is HIGH (see the registers
description). The default value of MCL15-MCL0 & MCH15-MCH0 bits is 42100d, which
gives a default count of 42100d CLK cycles. The value chosen for MCL15-MCL0 bits can
be different from the one of MCH15-MCH0 bits. This configurable count enables to
support ISO7816 and EMV compliant cards and to follow a potential standard change.
Let’s have a look to an asynchronous card activation and ATR. First, the application
starts the activation (START bit) after having configured the slot 1 (activation voltage).
The sequencer performs the activation sequence. The DC-to-DC converter is started,
then V
CC
goes to logic level one, I/O is enabled and CLK starts. RST is at logic level
zero.
Then the ATR counter checks the following steps:
1. If a start bit is detected on I/O during the first 200d CLK cycles, it is ignored and the
count goes on.
2. If a start bit is detected whilst RST is at logic level zero between 200d and 42100d
(or the value written in MCL15-MCL0 bits) CLK cycles, the bits EARLY and MUTE
are set to logic level one. RST will remain at logic level zero, it is up to the application
to decide whether accepting the card or not.
3. If no start bit has been detected until 42100d (or the value written in MCL15-MCL0
bits) CLK cycles, RST is set to logic level one.
4. If a start bit is detected within the first 370d (or 200d + the value written in EC7-EC0
bits) CLK cycles with RST at logic level one, the bit EARLY is set to logic level one.
5. If the card does not answer before 42100d (or the value written in MCH15-MCH0
bits)
