NXP Semiconductors PN7360AUEV, Руководство пользователя

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NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC Rev. 1.4 — 14 May 2018
314514
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3.4.2 Read operation
A read request cannot be handled within one AHB clock cycle, therefore wait states are
inserted by the AHB Slave Interface. The targeted EEPROM is 16-bit oriented so 32-bit
Read access need additional processing leading to additional wait states.
Table 3 gives
an overview of minimum idle time for a read operation.
Table 3. Wait states for read access on EEPROM
Address Width Wait states FAST mode Wait states SLOW mode
AHB clock
cycles 20 MHz clock AHB clock
cycles 20 MHz clock
32-bit 5 250 ns 7 350 ns
8/16-bit 2 100 ns 3 150 ns
3.5 Flash controller
The Flash is composed of two memory devices respectively controlled by one Flash
controller integrated twice in the EECTRL module. The main difference to the EEPROM
is a faster read access and a full-page programming.
3.5.1 Write operation
Write Access is done only with 32-bit access. A write operation cannot be handled within
one AHB clock cycle, therefore wait states are inserted by the AHB Slave Interface
during page register write phase. The following table gives an overview of minimum idle
time for a write operation. The Flash controllers program the Flash_0 and Flash_1 data
page by page.
A page register for write access is used to internally store the data in a quick way and
then a programming cycle is necessary to store the data.
Flash_0 stores data corresponding to «even» AHB addresses with bit [2] = ’0’ and
Flash_1 stores data corresponding to «odd» AHB addresses with bit [2] = ’1’.
Table 4. Wait states for write access on EEPROM
Address Width Wait states FAST mode Wait states SLOW mode
AHB clock
cycles ns (20 MHz clock) AHB clock
cycles
ns (20 MHz clock)
32-bit access 2 100 3 150
A write operation to the Flash has to be done in two steps:
1. Write the 64-Byte short term storage page register.
2. Program the page register in one row of the Flash matrix.
3.5.2 Read Operation
Even if 32-bit, 16-bit and 8-bit Read Access are supported at system level, read access
is only done with 32-bit accesses at memory level because the Flash is 32-bit oriented.
The read access is similar as for the EEPROM.
The following table gives idle time with AHB wait states insertion for a read operation