NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
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227 of 345
13.6.2.20 Register ct_toc_reg (Time-Out Configuration)
This configuration register is used for setting different configurations of the time-out
counter as given in
“Timer settings”
; all other configurations are undefined.
Table 268. ct_toc_reg (address 0058h) bit description
Bit
Symbol
Access
Reset
Value
Description
31:8
RESERVED
-
0
Reserved
7:0
TOC7 – TOC0
R/W
0000
0000b
Time-Out Configuration
Time-out counter mode selection (see table below).
Table 269. Timer settings
TOC Value
Operating Mode
00h
All counters are stopped
05h
Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter. Counters
2 and 3 are stopped; counter 1 continues to operate in auto-reload mode.
07h
Counters 1, 2 and 3 are three independent 8-bit counters. Counters 2 and 3 are stopped;
counter 1 continues to operate in auto-reload mode.
61h
Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value stored in
registers ct_tor3_reg and ct_tor2_reg is started after 61h is written in register ct_toc_reg. An
interrupt is given, and bit TO3 is set within register ct_usr2_reg when the terminal count is
reached. The counter is stopped by writing 00h in register ct_toc_reg, and sHALl be stopped
before reloading new values in registers ct_tor2_reg and ct_tor3_reg. In this configuration,
registers ct_tor3_reg and ct_tor2_reg must not be all zero.
65h
Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter. Counter 1
starts counting the content of register ct_tor1_reg on the first start bit (reception or transmission)
detected on pin I/O after 65h is written in register ct_toc_reg. When counter 1 reaches its
terminal count, an interrupt is given, bit TO1 in register ct_usr2_reg is set, and the counter
automatically restarts the same count until it is stopped. Changing the content of register
ct_tor1_reg during a count is not allowed. Counting the value stored in registers ct_tor3_reg and
ct_tor2_reg is started after 65H is written in register ct_toc_reg. When the counter reaches its
terminal count, an interrupt is given and bit TO3 is set within register ct_usr2_reg. Both counters
are stopped when 00H is written in register ct_toc_reg. Counters 3 and 2 sHALl be stopped by
writing 05h in register ct_toc_reg before reloading new values in registers ct_tor2_reg and
ct_tor3_reg. In this configuration, registers ct_tor3_reg, ct_tor2_reg and ct_tor1_reg must not be
all zero.
71h
Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value stored in
registers ct_tor3_reg and ct_tor2_reg is started on the first start bit detected on pin I/O
(reception or transmission) after the value has been written, and then on each subsequent start
bit. It is possible to change the content of registers ct_tor3_reg and ct_tor2_reg during a count;
the current count will not be affected and the new count value will be taken into account at the
next start bit. An interrupt is given, and bit TO3 is set within register ct_usr2_reg when the
terminal count is reached. The counter is stopped by writing 00h in ct_toc_reg register. In this
configuration, registers ct_tor3_reg and ct_tor2_reg must not be all zero.
73h
Counters 1, 2 and 3 are three independent 8-bit counters. Counter 1 is stopped. Counter 2
starts counting the content of register ct_tor2_reg on the first start bit (reception or transmission)
detected on pin I/O after 73h is written in register ct_toc_reg, and then on each subsequent
start bit. It is possible to change the content of register ct_tor2_reg during a count; the current
