NXP Semiconductors PN7360AUEV, Руководство пользователя

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NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC Rev. 1.4 — 14 May 2018
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7.6.3 PLL N and P decoded divider ratio
The CLKGEN_USB_PLL_NDEC_PDEC_WO_SOFTDEC_REG register contains the
USB PLL multiplier and divider values. Changes to
CLKGEN_USB_PLL_NDEC_PDEC_WO_SOFTDEC register do not take effect until a
correct USB feed sequence has been given (see
Section 7.2 ). Calculations for the USB
PLL frequency, and multiplier and divider values are found in Section 7.2 .
Table 59. CLKGEN_USB_PLL_NDEC_PDEC_WO_SOFTDEC_REG (address 0014h)
Bit Symbol Access Value Description
31:16 RESERVED R/W 0x00 Reserved
15:10 USB_PDEC_WO_SOFTDEC R/W 0x00 divider ratio code for P-divider when soft decoder is not
used
9:0 USB_NDEC_WO_SOFTDEC R/W 0x00 divider ratio code for N-divider when soft decoder is not
used
7.7 CLIF PLL register description
CLIF PLL is controlled by the registers shown in Table 60 . More detailed descriptions
follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic
zero.
Warning: Improper setting of CLIF PLL values may result in incorrect operation of
the Contactless System!
Table 60. CLIF PLL register overview
Name Address
offset Width
(bits) Access Reset value Description
CLKGEN_CLIF_PLL1_CONTRO
L_REG 0018h 32 R/W 02E3B190h Clif pll usage configurations
CLKGEN_CLIF_PLL2_CONTRO
L_REG 001Ch 32 R/W 02E121E0h Clif pll usage configurations
CLKGEN_CLIF_PLL_GLOBAL_
CONTROL_REG 0020h 32 R/W 000000C0h Clif pll integration configurations
CLKGEN_INPUT_CLOCK_DETE
CTOR_CONTROL_REG 0024h 32 R/W 000011ADh input clock detector control
CLKGEN_CLOCK_PRESENCE_
BYPASS_REG 002Ch 32 R/W 0000000Fh yes clock presence for clif_pll
7.7.1 CLIF PLL CONTROL1 REG
The CLKGEN_CLIF_PLL1_CONTROL_REG register contains the CLIF PLL multiplier
and divider values. Changes to CLKGEN_CLIF_PLL1_CONTROL_REG register do not
take effect until a correct CLIF PLL feed sequence has been given. Calculations for the
USB PLL frequency, and multiplier and divider values are found in
Section 7.2 .