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IEEE 1149.1 Test Access Port (JTAG)
MCF5253 Reference Manual, Rev. 1
21-6
Freescale Semiconductor
21.5
JTAG Register Definitions
21.5.1
JTAG Instruction Shift Register
The MCF5253 IEEE 1149.1A Standard implementation uses a 4-bit instruction-shift register without
parity. This register transfers its value to a parallel hold register and applies one of eight possible
instructions on the falling edge of TCK when the TAP state machine is in the update-IR state. To load the
instructions into the shift portion of the register, place the serial data on the TDI pin prior to each rising
edge of TCK.
lists the public, usable instructions that are supported along with their encoding.
The IEEE 1149.1A Standard requires the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions.
IDCODE, CLAMP, HIGHZ are optional standard instructions that the MCF5253 implementation supports
and are described in the IEEE Standard 1149.1A. The RINGOSC and ORGATE are user defined
instructions only used for device test during manufacturing.
21.5.1.1
EXTEST Instruction
The external test instruction (EXTEST) selects the boundary-scan register. The EXTEST instruction
forces all output pins and bidirectional pins configured as outputs to the preloaded fixed values (with the
SAMPLE/PRELOAD instruction) and held in the boundary-scan update registers. The EXTEST
instruction can also configure the direction of bidirectional pins and establish high-impedance states on
some pins. The EXTEST instruction becomes active on the falling edge of TCK in the update-IR state
when the data held in the instruction-shift register is equivalent to hex 0.
21.5.1.2
IDCODE
The IDCODE instruction selects the 32-bit IDcode register for connection as a shift path between the TDI
pin and the TDO pin. This instruction lets users interrogate the MCF5253 to determine its version number
Table 21-2. JTAG Instructions
Instruction ABBR Class
IR[3:0]
Instruction Summary
EXTEST
EXT
Required
0000
Select BS register while applying fixed values to output pins and asserting functional
reset
IDCODE
IDC
Optional
0001
Selects IDCODE register for shift
SAMPLE/
PRELOAD
SMP
Required
0010
Selects BS register for shift, sample, and preload without disturbing functional
operation
CLAMP
CMP
Optional
0011
Selects bypass while applying fixed values to output pins and asserting functional
reset
HIGHZ
HI_Z
Optional
0100
Selects the bypass register while tri-stating all output pins and asserting functional
reset
RINGOSC
RING
Optional
0111
User defined function for device test
ORGATE
OR
Optional
1000
User defined function for device test
BYPASS
BYP
Required
1111
Selects the bypass register for data operations
Содержание MCF5253
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