NXP Semiconductors MCF5253, Справочное руководство

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Synchronous DRAM Controller Module
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 7-17
The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to the
SDRAM address space generates the
MRS
command to that SDRAM. The address of the access should be
selected to place the correct mode information on the SDRAM address pins. The address is not multiplexed
for the
MRS
command. The
MRS
access can be a read or write. The important thing is that the address output
of that access needs the correct mode programming information on the correct address bits.
Figure 7-12 shows the
MRS
command, which occurs in the first clock of the bus cycle.
Figure 7-12. Mode Register Set (
MRS
) Command
7.6 SDRAM Example
This example interfaces a Samsung K4S641633 1M x 16-bit x 4 bank SDRAM component to a MCF5253
operating at 80 MHz (40 MHz bus).
Table 7-12 lists design specifications for this example.
Table 7-12. SDRAM Example Specifications
Parameter Specification
12 rows, 8 columns –
Two bank-select lines to access four internal banks –
ACTV
-to-read/write delay (t
RCD
) 20 nS (min.)
Period between auto refresh and
ACTV
command (t
RC
) 70 nS
ACTV
command to precharge command (t
RAS
) 48 nS (min.)
Precharge command to
ACTV
command (t
RP
) 20 nS (min.)
Last data input to
PALL
command (t
RWL
) 1 bus clock (25 nS)
Auto refresh period for 4096 rows (t
REF
) 64 mS
A[31:0]
SDRAS, SDCAS
SDWE
D[31:16]
MRS
SD_CS0
BCLK