Analog-to-Digital Converter (ADC12)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
15-9
If the MODE bits are changed, any data in ADCRH becomes invalid.
15.3.4
Data Result Low Register (ADCRL)
ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an
8-bit conversion. This register is updated each time a conversion completes except when automatic
compare is enabled and the compare condition is not met. In 12-bit and 10-bit mode, reading ADCRH
prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL
is read. If ADCRL is not read until the after next conversion is completed, the intermediate conversion
results are lost. In 8-bit mode, there is no interlocking with ADCRH. If the MODE bits are changed, any
data in ADCRL becomes invalid.
15.3.5
Compare Value High Register (ADCCVH)
In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. These bits
are compared to the upper four bits of the result following a conversion in 12-bit mode when the compare
function is enabled.
7
6
5
4
3
2
1
0
R
0
0
0
0
ADR11
ADR10
ADR9
ADR8
W
Reset:
0
0
0
0
0
0
0
0
Figure 15-4. Data Result High Register (ADCRH)
7
6
5
4
3
2
1
0
R
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
W
Reset:
0
0
0
0
0
0
0
0
Figure 15-5. Data Result Low Register (ADCRL)
7
6
5
4
3
2
1
0
R
0
0
0
0
ADCV11
ADCV10
ADCV9
ADCV8
W
Reset:
0
0
0
0
0
0
0
0
Figure 15-6. Compare Value High Register (ADCCVH)
