Timer/PWM Module (TPM)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
19-16
Writes to any of TPMxCnVH and TPMxCnVL registers actually write to buffer registers. In output
compare mode, the TPMxCnVH:TPMxCnVL registers are updated with the value of their write buffer
only after both bytes were written and according to the value of CLKSB:CLKSA bits:
•
If CLKSB and CLKSA are cleared, the registers are updated when the second byte is written
•
If CLKSB and CLKSA are not cleared, the registers are updated at the next change of the TPM
counter (end of the prescaler counting) after the second byte is written.
The coherency sequence can be manually reset by writing to the channel status/control register
(TPMxCnSC).
An output compare event sets a flag bit (CHnF) that optionally generates a CPU interrupt request.
19.4.2.3
Edge-Aligned PWM Mode
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can
be used when other channels in the same TPM are configured for input capture or output compare
functions. The period of this PWM signal is determined by the value of the modulus register
(TPMxMODH:TPMxMODL) plus 1. The duty cycle is determined by the value of the timer channel
register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by ELSnA bit. 0% and
100% duty cycle cases are possible.
The time between the modulus overflow and the channel match value (TPMxCnVH:TPMxCnVL) is the
pulse width or duty cycle (
). If ELSnA is cleared, the counter overflow forces the PWM signal
high, and the channel match forces the PWM signal low. If ELSnA is set, the counter overflow forces the
PWM signal low, and the channel match forces the PWM signal high.
Figure 19-14. EPWM period and pulse width (ELSnA=0)
When the channel value register is set to 0x0000, the duty cycle is 0%. A 100% duty cycle is achieved by
setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting.
This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle.
The timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM
pulse widths. Writes to any of the registers TPMxCnVH and TPMxCnVL actually write to buffer registers.
In edge-aligned PWM mode, the TPMxCnVH:TPMxCnVL registers are updated with the value of their
write buffer according to the value of CLKSB:CLKSA bits:
•
If CLKSB and CLKSA are cleared, the registers are updated when the second byte is written
•
If CLKSB and CLKSA are not cleared, the registers are updated after both bytes were written, and
the TPM counter changes from (TPMxMODH:TPMxMODL – 1) to
period
pulse width
overflow
overflow
overflow
channel
match
channel
match
channel
match
TPMxCHn
