Mini-FlexBus
11-19
Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
11.4.6.4.2
Address Setup and Hold
The timing of the assertion and negation of the chip selects, byte selects, and output enable can be
programmed on a chip-select basis. Each chip-select can be programmed to assert one to four clocks after
address-latch enable (FB_ALE) is asserted.
show read- and write-bus
cycles with two clocks of address setup.
Figure 11-18. Read-Bus Cycle with Two-Clock Address Setup (No Wait States)
Figure 11-19. Write-Bus Cycle with Two Clock Address Setup (No Wait States)
FB_CLK
FB_R/W
FB_ALE
S0
AS
S1
S2
S3
DATA
DATA
Mux’d Bus
Non-Mux’d Bus
FB_A[19:0]
ADDR[19:0]
FB_D[7:0]
ADDR[
X
:0]
FB_AD[19:
X+1
]
ADDR[19:
X+1
]
FB_AD[
X
:0]
FB_CS
n
, FB_OE
S0
FB_CLK
FB_R/W
FB_ALE
FB_OE
S0
AS
S1
S2
S3
DATA
DATA
Mux’d Bus
Non-Mux’d Bus
FB_A[19:0]
ADDR[19:0]
FB_D[7:0]
ADDR[
X
:0]
FB_AD[19:
X+1
]
ADDR[19:
X+1
]
FB_AD[
X
:0]
FB_CS
n
S0
