Multipurpose Clock Generator (MCG)
MCF51CN128 Reference Manual, Rev. 6
6-26
Freescale Semiconductor
6.5.3.3
Example 3: Moving from BLPI to FEE Mode: External Crystal = 8 MHz,
Bus Frequency = 16 MHz
In this example, the MCG moves through the proper operational modes from BLPI mode at a 16 kHz bus
frequency running off of the internal reference clock (see previous example) to FEE mode using an 8MHz
crystal configured for a 16 MHz bus frequency. First, the code sequence is described. Then a flowchart is
included that illustrates the sequence.
1. First, BLPI must transition to FBI mode.
a) MCGC2 = 0x00 (%00000000)
– LP (bit 3) in MCGSC is 0
b) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has acquired
lock. Although the FLL is bypassed in FBI mode, it remains enabled and running.
2. Next, FBI transitions to FEE mode.
a) MCGC2 = 0x36 (%00110110)
– RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure the crystal oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
has been initialized.
c) MCGC1 = 0x18 (%00011000)
– CLKS (bits 7 and 6) set to %00 to select the output of the FLL as system clock source
– RDIV (bits 5-3) remain at %011, or divide-by-256 for a reference of 8 MHz / 256 = 31.25
kHz.
– IREFS (bit 1) cleared to 0, selecting the external reference clock
d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference clock is the current
source for the reference clock
e) Optionally, loop until LOCK (bit 6) in the MCGSC is set, indicating that the FLL has
reacquired lock.
f) Loop until CLKST (bits 3 and 2) in MCGSC are %00, indicating that the output of the FLL is
selected to feed MCGOUT
g) Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 512, and a bus divider
of 1, MCGOUT = 31.25 kHz * 512 / 1 = 16 MHz. Therefore, the bus frequency is 8 MHz.
h) At this point, by default, the DRS[1:0] bits in MCGC4 are set to %00 and DMX32 in MCGC4
is cleared to 0. If a bus frequency of 16MHz is desired instead, set the DRS[1:0] bits to 0x01
to switch the FLL multiplication factor from 512 to 1024 and loop until LOCK (bit 6) in
MCGSC is set, indicating that the FLL has reacquired LOCK. To return the bus frequency to 8
MHz, set the DRS[1:0] bits to %00 again, and the FLL multiplication factor switches back to
512. Then loop again until the LOCK bit is set.
